US3737632A
Expired / Lapsed
US
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Rate adaptive nonsynchronous demodulator apparatus for biphase binary signals
Assignee: Individual
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Filing: 1972-03-23
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Granted: 1973-06-05
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Expires: 1992-03-23
Abstract
Abstract A demodulator apparatus is described for demodulating nonsynchronous binary input signals of the two level biphase type having a nonuniform bit rate. The demodulator comprises a reference means including a first digital counter which measures the width of successive input bits and produces time reference signals corresponding thereto so that the magnitude of such reference signal is automatically changed in response to variation in the bit rate. A comparator means including a second counter and discriminator is employed for comparing the reference signal of the preceding input bit against the time interval of the biphase information portion of the next succeeding input bit to determine whether it is a binary one or a binary zero. By employing this dynamic reference technique to compensate for varying bit rates in the nonsynchronous biphase input signal, one embodiment of the demodulator employing sixteen stage binary counters has been operated over a nonsynchronous bit rate range of 10 to 40,000 bits per second where the change in bit rate between adjacent bits can be between +20 and -35 percent.
Inventors
- 👤 R Barnes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:58
CPC Classifications
G; G06; G06K; G06K7/00; G06K7/01; G06K7/016; G06K7/0166
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
181 words
A nonsynchronous demodulator apparatus in which the improvement comprises: input means for supplying to the input of the demodulator a series binary input signal of two level nonsynchronous binary encoded input bits of biphase type having a non-uniform bit rate; reference means for determining the width of successive ones of said input bits, and for producing a time reference signal corresponding to the width of each input bit so that the value of said reference signal is automatically changed in response to changes in the width of said input bits due to variations in the bit rate; comparator means including a discriminator means, for comparing the reference signal corresponding to the width of the next preceding input bit against the time interval of the biphase binary information portion of the next succeeding bit to determine whether said succeeding bit is a binary one or a binary zero; and output means connected to said discriminator means for producing at the output of the demodulator a series binary output signal of output bits corresponding to said input bits but of a different code.
Claim 2
Dependent Claim
181 words
A nonsynchronous demodulator apparatus in which the improvement comprises: input means for supplying to the input of the demodulator a series binary input signal of two level nonsynchronous binary encoded input bits of biphase type having a non-uniform bit rate; reference means for determining the width of successive ones of said input bits, and for producing a time reference signal corresponding to the width of each input bit so that the value of said reference signal is automatically changed in response to changes in the width of said input bits due to variations in the bit rate; comparator means including a discriminator means, for comparing the reference signal corresponding to the width of the next preceding input bit against the time interval of the biphase binary information portion of the next succeeding bit to determine whether said succeeding bit is a binary one or a binary zero; and output means connected to said discriminator means for producing at the output of the demodulator a series binary output signal of output bits corresponding to said input bits but of a different code.
Claim 3
Dependent Claim
67 words
A demodulator apparatus in accordance with claim 1 in which the discriminator means discriminates between regular and irregular transitions in the biphase binary input signal and applies timing pulses to said reference means which correspond only to said regular transitions in order to produce said time reference signal, and for transmitting information pulses to said output means corresponding only to irregular transitions to produce said output signal.
Claim 4
Dependent Claim
37 words
A demodulator apparatus in accordance with claim 2 in which the output means includes an output memory means having at least one bistable multivibrator which is triggered by said information pulses in response to said irregular transitions.
Claim 5
Dependent Claim
70 words
A demodulator apparatus in accordance with claim 2 in which the reference means includes a first digital counter and the comparator means includes a second digital counter, and a standard pulser means for applying to the inputs of said first and second counters standard pulses of a predetermined frequency with the standard pulses applied to said first counter being of a lower frequency than those applied to the second counter.
Claim 6
Dependent Claim
95 words
A demodulator apparatus in accordance with claim 4 which also includes a transfer means for transferring said reference signal from said first counter to said second counter upon receipt of the next input bit to preset said second counter to the complement voltage value of said reference signal so that said second counter produces an output only after counting a number of standard pulses exceeding said complement of the reference signal previously counted in the first counter, and means for setting said first counter to zero after a time delay with respect to said transfer.
Claim 7
Dependent Claim
74 words
A demodulator apparatus in accordance with claim 5 in which the input means includes a sequential control means which is operated in response to the receipt of an input pulse corresponding To a regular transition of said input signal for disabling the first counter and actuating the transfer means, for resetting said first counter to zero after a first delay and for actuating the discriminator means after a second delay in the sequence mentioned.
Claim 8
Dependent Claim
48 words
A demodulator apparatus in accordance with claim 6 in which the sequential control means includes a first monostable multivibrator connected between its input and the reset terminals of the first counter, and a second monostable multivibrator connected between the output of said first multivibrator and said discriminating means.
Claim 9
Dependent Claim
79 words
A demodulator apparatus in accordance with claim 7 in which the input memory means includes a pair of interconnected bistable multivibrators connected to a first gate means for transmitting input pulses corresponding to the beginning and end of a preamble bit directly to the sequential control means, and input pulses corresponding to other regular transitions of the input signal through a second gate means to said control means when said second gate means is enabled by the discriminator means.
Claim 10
Dependent Claim
101 words
A demodulator apparatus in accordance with claim 4 in which the discriminator means includes a bistable multivibrator triggered by the output of the second counter and reset after the next regular transition of the input signal to produce a disabling signal which is applied to one input of an And gate having its other input connected to receive input pulses corresponding to regular and irregular transitions of the input signal so that only the irregular transition pulses occurring before the second counter output are transmitted through said And gate to the output of the discriminator means to provide the information pulses.
Claim 11
Dependent Claim
106 words
A demodulator apparatus in accordance with claim 9 in which the comparator means also includes a third digital counter connected to the output of said standard pulser means for applying to said third counter standard pulses of a lower frequency than those applied to the first counter, said third counter also being connected to the output of said transfer means and producing an End pulse at the end of each group of input bits corresponding to a word or character when the interval between successive transitions of the input signal exceeds by a predetermined amount proportional to the width of the last bit of said group.
Claim 12
Dependent Claim
46 words
A demodulator apparatus in accordance with claim 10 in which the input means includes a input memory means for resetting all of the counters upon receipt of said End pulse and thereafter enabling said counters in response to the next regular transition of the input signal.
Claim 13
Dependent Claim
88 words
A demodulator apparatus in accordance with claim 1 in which the input means provides said input signal with bits arranged in separate groups of bits with each group including a preamble bit at the beginning, a plurality of information bits and a termination space at the end of said group, said preamble bit having a width substantially the same as that of the first information bit and said termination space having an interval at least 1 1/2 times the width of the last information bit of the group.
Claim 14
Dependent Claim
50 words
A demodulator apparatus in accordance with claim 1 in which the input means includes an optical reader, a label having a plurality of light reflective and nonreflective bars arranged in binary code, and means for scanning said reader across said bars at a nonuniform rate to produce said input signal.
Claim 15
Dependent Claim
29 words
A demodulator apparatus in accordance with claim 8 in which the binary coded information on said label includes the price of an item to which the label is attached.
Claim 16
Dependent Claim
19 words
A demodulator apparatus in accordance with claim 1 in which the output means is connected to a digital computor.
Claim 17
Dependent Claim
41 words
A demodulator apparatus in accordance with claim 1 in which the input means includes a magnetic reader, a magnetic record of binary information, and means for scanning said reader across said record at a nonuniform rate to produce said input signal.
Claim 18
Dependent Claim
29 words
A demodUlator apparatus in accordance with claim 1 which also includes means for producing bit sync output pulses that are synchronized with the information bits of the output signal.
References Cited (Backward Citations)
US3514706A
Cited
US3597752A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-06-04 | 1976-12-04 | 1977-06-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-06-04 | 1980-12-04 | 1981-06-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-06-04 | 1984-12-04 | 1985-06-05 | $7700.00 | Window Closed / Lapsed |