US3736192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Integrated circuit and method of making the same
Assignee: Hitachi Ltd
•
Filing: 1969-12-03
•
Granted: 1973-05-29
•
Expires: 1989-12-03
Abstract
Abstract AN INTEGRATED CIRCUIT COMPRISING A SEMICONDUCTOR EPITAXIAL LAYER HAVING TWO OR MORE SEMICONDUCTOR CIRCUIT ELEPAYMENTS SUCH AS A TRANSISTOR, DIODE AND RESISTO FORMED ON ONE SURFACE THEREOF, AND A HIGH RESISTIVITY REGION FORMED BY IMPLANTATION OF IONS FROM THE SURFACE OF THE EPITAXIAL LAYER, THE SEMICONDUCTOR CIRCUIT ELEMENTS BEING ELECTRICALLY DIVIDED INTO A PLURALITY OF GROUPS BY THE HIGH RESISTIVITY REGION OF THE EPITAXIAL LAYER FORMED BY ION IMPLNTATION.
Inventors
- 👤 T Tokuyama
- 👤 T Tsuchimoto
- 👤 T Ikeda
- 👤 S Nishimatsu
- 👤 H Sano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:20
CPC Classifications
H; H10; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; H10P95/00; H10W; H10W10/00; H10W10/01
Claims Analysis
Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-05-28 | 1976-11-27 | 1977-05-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-05-28 | 1980-11-27 | 1981-05-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-05-28 | 1984-11-27 | 1985-05-29 | $7700.00 | Window Closed / Lapsed |