US3729586A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital guard-time circuit for use in a frame synchronization circuit
Assignee: Nortel Networks Ltd
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Filing: 1971-09-23
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Granted: 1973-04-24
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Expires: 1991-09-23
Abstract
Abstract A digital counter is responsive to framing error pulses for providing a signal after a predetermined number of error pulses have been counted within a predetermined interval of time. Access to the counter by the error pulses is controlled by a first retriggerable monostable multivibrator which has a time constant greater than the time duraction of one frame and less than the time duration of N frames, where N is determined by the forward guard-time and the tolerable mis-frame rate of the system. The signal from the counter is used to trigger on a second retriggerable monostable multivibrator which determines the backward guard-time of the circuit and controls the sending of reframing pulses to a reframing circuit.
Inventors
- 👤 Q Chow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:04
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/0602; H04J3/0605; H04J3/0608; H04J3/14
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
166 words
In a frame synchronization circuit for a digital transmission system, wherein each frame has the same predetermined time duration, said frame synchronization circuit having a framing error detection circuit for providing framing error pulses and a reframing circuit for resynchronizing the system, a guard-time circuit comprising: a digital counter means responsive to said framing error pulses for providing a signal when a predetermined number of error pulses have been counted within a predetermined interval of time, a first means responsive to said framing error pulses for enabling said counter means to receive said framing error pulses and for resetting said counter means when said predetermined number of consecutive error pulses have been counted within said predetermined interval of time and when the number of error pulses does not reach said predetermined number within said predetermined interval of time, and a second means responsive to said signal for providing reframe pulses to the reframing circuiT, each of said reframe pulses corresponding to each subsequent framing error pulse.
Claim 2
Dependent Claim
166 words
In a frame synchronization circuit for a digital transmission system, wherein each frame has the same predetermined time duration, said frame synchronization circuit having a framing error detection circuit for providing framing error pulses and a reframing circuit for resynchronizing the system, a guard-time circuit comprising: a digital counter means responsive to said framing error pulses for providing a signal when a predetermined number of error pulses have been counted within a predetermined interval of time, a first means responsive to said framing error pulses for enabling said counter means to receive said framing error pulses and for resetting said counter means when said predetermined number of consecutive error pulses have been counted within said predetermined interval of time and when the number of error pulses does not reach said predetermined number within said predetermined interval of time, and a second means responsive to said signal for providing reframe pulses to the reframing circuiT, each of said reframe pulses corresponding to each subsequent framing error pulse.
Claim 3
Dependent Claim
80 words
A guard-time circuit as defined in claim 1, wherein said first means comprises: a first retriggerable monostable multivibrator having a time constant longer than the time duration of one of said frames and shorter than the time duration of N frames, where N is determined by the forward guard-time and the tolerable mis-frame rate of the system, a first gate means responsive to said framing error pulses and a first output of said first multivibrator for pulsing said counter means.
Claim 4
Dependent Claim
118 words
A guard-time circuit as defined in claim 2 wherein said second means comprises: a second retriggerable monostable multivibrator having a time constant equal to the time duration of a plurality of said frames, a second gate means responsive to a first output of said second monostable and to said error pulses for providing said reframing pulses, an orring gate means responsive to said signal and to the reframe pulses for triggering said second monostable, and a third gate means responsive to a second output of said second monostable and to said framing error pulses for triggering said first monostable and for preventing access of said framing error pulses to said first monostable after the occurrence of said signal.
Claim 5
Dependent Claim
16 words
A guard-time circuit as defined in claim 3, wherein said counter means is a binary counter.
References Cited (Backward Citations)
US3144515A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-04-23 | 1976-10-23 | 1977-04-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-04-23 | 1980-10-23 | 1981-04-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-04-23 | 1984-10-23 | 1985-04-24 | $7700.00 | Window Closed / Lapsed |