Alignment and bonding method for semiconductor components

Claim 2

An alignment and bonding method for mounting each of a plurality of semiconductor structures to each of a plurality of lead structures where the semiconductor structures are of the type including semiconductor devices and having bonding pads arranged in a predetermined pattern and where the lead structures are of the type having a plurality of spaced leads arranged in the predetermined pattern of the semiconductor bonding pads comprising the steps of placing the plurality of semiconductor structures respectively on a carrier having a plurality of perforations smaller than the semiconductor structures so that a perforation underlies each of the semiconductor structures, successively positioning the carrier to position, one at a time, each semiconductor structure in spaced aligned relationship with one of the plurality of lead structures, successively detaching each spaced aligned semiconductor structure from the carrier by support means passing through the perforation in the die carrier underlying the aligned semiconductor structure, carrying the semiconductor structure by these support means to the lead structure so that the plurality of bonding pads mate with the plurality of spaced leads, and bonding the bonding pads to the spaced leads.

Claim 3

A method as in claim 1 wherein the carrier is positioned to position one of the semiconductor structures at a bonding position and including the step of positioning the plurality of lead structures to position one of the lead structures at the bonding position in spaced aligned relationship to the semiconductor structure at the bonding position.

Claim 4

A method as in claim 1 including the step of rotating and translating as necessary the support means and hence the semiconductor structure carried thereby to exactly align bonding pads on the semiconductor structure with leads of the lead structure.

Claim 5

An alignment and bonding method for mounting each of a plurality of semiconductor structures to each of a plurality of lead structures where the semiconductor structures are of the type including semiconductor devices and having bonding pads arranged in a predetermined pattern, which plurality of semiconductor structures are formed spaced on predetermined centers in an array in a semiconductor wafer and where the lead structures are of the type having a plurality of spaced leads arranged in the predetermined pattern of the semiconductor bonding pads, comprising the steps of aligning the semiconductor wafer with a die carrier having an array of perforations formed therein and spaced on the predetermined centers such that each of the semiconductor structures is aligned with one of the perforations, adhesively securing the aligned semiconductor wafer to the die carrier, separating the semiconductor wafer into individual semiconductor structures with each semiconductor structure being adhesively retained on the die carrier, successively positioning the die carrier to position, one at a time, each semiconductor structure in spaced, aligned relationship with one of the plurality of lead structures, successively detaching each sPaced aligned semiconductor structure from the die carrier by support means passing through the perforation in the die carrier underlying the aligned semiconductor structure, carrying the semiconductor structure by the support means to the lead structures so that the plurality of the bonding pads mate with the plurality of spaced leads, and bonding the bonding pads to the spaced leads.

Claim 6

An alignment and bonding method for mounting each of a plurality of semiconductor structures to each of a plurality of lead structures where the semiconductor structures are of the type including semiconductor devices and having bonding pads arranged in a predetermined pattern, which plurality of semiconductor structures are formed spaced on predetermined centers in an array in a semiconductor wafer and where the lead structures are of the type having a plurality of spaced leads arranged in the predetermined pattern of the semiconductor bonding pads, comprising the steps of aligning the semiconductor wafer with a die carrier having an array of perforations formed therein and spaced on the predetermined centers such that each of the semiconductor structures is aligned with one of the perforations, adhesively securing the aligned semiconductor wafer to the die carrier, separating the semiconductor wafer into individual semiconductor structures with each semiconductor structure being adhesively retained on the die carrier, successively positioning the die carrier to position, one at a time, each semiconductor structure in spaced, aligned relationship with one of the plurality of lead structures, successively detaching each sPaced aligned semiconductor structure from the die carrier by support means passing through the perforation in the die carrier underlying the aligned semiconductor structure, carrying the semiconductor structure by the support means to the lead structures so that the plurality of the bonding pads mate with the plurality of spaced leads, and bonding the bonding pads to the spaced leads.

Claim 7

A method as in claim 4 wherein the die carrier is positioned to position one of the semiconductor structures at a bonding position and including the step of positioning the plurality of lead structures to position one of the lead structures at the bonding position in spaced aligned relationship with the semiconductor structure at the bonding position.

Claim 8

A method as in claim 5 wherein a plurality of lead structures are retained in an aligned array so that when the aligned array of lead structures is positioned to position one of the lead structures at the bonding position, the spaced leads of that lead structure are in alignment with the bonding pads of the semiconductor structure positioned at the bonding position.

Claim 9

A method as in claim 4 wherein the aligned semiconductor wafer is adhesively secured to the die carrier with a heat sensitive adhesive and including the step of heating the support means to facilitate detaching each spaced aligned semiconductor structure from the die carrier.

Claim 10

A method as in claim 4 wherein the support means has a vacuum face and including the step of applying vacuum thereto for holding a semiconductor structure to the support means while the support means carries the semiconductor structure to the lead structure.

Claim 11

A method as in claim 4 wherein the semiconductor structure while it is being carried by the support means is guided by a guide structure interposed between the die carrier and the plurality of lead structures.