US3721961A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data processing subsystems
Assignee: International Business Machines Corp
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Filing: 1971-08-11
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Granted: 1973-03-20
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Expires: 1991-08-11
Abstract
Abstract Data processing peripheral subsystems are connectable to two different types of data processing systems, each having different capabilities. For example, one data processing system Type 1 has certain error recovery procedures which are greater and more effective than those available for Type 2. The peripheral subsystem detects the type of data processing system to which it is attached and adjusts its operational procedures for emulating the operation of a Type 2 data processing system to the operational capabilities of the Type 1 data processing system without internal changes within the data processing system. The peripheral subsystem is further adapted to operate in a degraded mode with a data processing system of either type when the situation demands it.
Inventors
- 👤 G Edstrom
- 👤 R Elwell
- 👤 J Irwin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:05
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0727; G06F11/0745; G06F11/0793; G06F13/00; G06F13/38; G06F13/382; G06F13/387
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
183 words
For a data processing system, a first peripheral unit adapted to be connected with first or second classes of CPU''s, the classes having differing operational capabilities; the first class of CPU''s being responsive to a given status signal from the first unit to initiate in said first unit a first action followed by a second action, said second class of CPU''s not being responsive to said given status signal but being responsive to a second status signal indicating another status to initiate said second action in the first unit; the improvement in said first unit including the combination: first means establishing said given status signal, second means establishing which class of CPU''s will be operatively associated with said given status signal, and third means jointly responsive to said first and second means either to supply said given status to said first class CPU or to supply said second status signal to said second class CPU while simultaneously independently initiating said first action in said first unit while preventing said second action by said second class CPU until completion of said independent first action.
Claim 2
Dependent Claim
183 words
For a data processing system, a first peripheral unit adapted to be connected with first or second classes of CPU''s, the classes having differing operational capabilities; the first class of CPU''s being responsive to a given status signal from the first unit to initiate in said first unit a first action followed by a second action, said second class of CPU''s not being responsive to said given status signal but being responsive to a second status signal indicating another status to initiate said second action in the first unit; the improvement in said first unit including the combination: first means establishing said given status signal, second means establishing which class of CPU''s will be operatively associated with said given status signal, and third means jointly responsive to said first and second means either to supply said given status to said first class CPU or to supply said second status signal to said second class CPU while simultaneously independently initiating said first action in said first unit while preventing said second action by said second class CPU until completion of said independent first action.
Claim 3
Dependent Claim
40 words
The unit set forth in claim 1 wherein said given status signals represent an error condition associated with said first unit, and said second status signal indicates an error condition in signals received by said first unit from said CPU''s.
Claim 4
Dependent Claim
30 words
The unit set forth in claim 2 wherein said first action is SELECTIVE RESET (SELRST) and said second action is RETRY of a previous unsuccessful operation by said first unit.
Claim 5
Dependent Claim
50 words
A system including the unit set forth in claim 3 further including a peripheral device connected to said first unit and operative within said first unit to perform signal-processing functions related to functions performed in either class of CPU and said given status signal resulting from a hardware error condition.
Claim 6
Dependent Claim
39 words
The system set forth in claim 4 further adapted to operate with two CPU''s via switching means controlled by said CPU''s, said second means being further responsive to said switching mean to ascertain in which class either CPU resides.
Claim 7
Dependent Claim
93 words
The system set forth in claim 4 wherein channel means interconnect said second class CPU and said first unit, said second status signal indicating an error condition in said channel means detected by said first unit, and a second class of peripheral units not having self-initiatable SELRST connectable via said channel means to said CPU''s and operative with said second status signal to RETRY only said channel means error conditions with said second class CPU''s while said first unit is capable of attempting recovery from additional error conditions over said same channel means.
Claim 8
Dependent Claim
97 words
The system set forth in claim 4 further including either first channel means or second channel means for respectively connecting said first unit to said first or second class CPU''s, said first channel means adapted to receive DISCONNECT IN from said first unit and supplying an SELRST command to said first unit immediately followed by a COMMAND RETRY for effecting said second action of retrying a previously attempted operation, and said second channel means not capable of responding to said DISCONNECT IN but capable of attempting a data processing operation in respOnse to said second class CPU.
Claim 9
Independent Claim
217 words
The method of enhancing total system operation by selected sequences in a peripheral subsystem, said system including at least one CPU of given operational capability, said selected sequences in said peripheral subsystem effect on total system operation being similar with respect thereto for predetermined actions irrespective of first or second CPU''s of differing capabilities in said total system and which control said subsystem via a predetermined interface, the following steps in combination: establishing a signal condition and indication in the peripheral subsystem of the given capability of a connected and controlling CPU, establishing and executing a short sequence of operations in said subsystem for a first capability controlling CPU including a sequence of responsive steps to a series of commands from such controlling CPU, and establishing and executing a long sequence of operations in said subsystem for a second capability controlling CPU, including sending a status signal in said long sequence to such second controlling CPU indicating an operational state in said interface detected by said subsystem, causing said second controlling CPU to initiate an action in said subsystem functionally equivalent of cooperative action in said short sequence between said first capability controlling CPU and the subsystem whereby the total operational capability of said second controlling CPU is effectively enhanced to that of said first controlling CPU.
Claim 10
Independent Claim
217 words
The method of enhancing total system operation by selected sequences in a peripheral subsystem, said system including at least one CPU of given operational capability, said selected sequences in said peripheral subsystem effect on total system operation being similar with respect thereto for predetermined actions irrespective of first or second CPU''s of differing capabilities in said total system and which control said subsystem via a predetermined interface, the following steps in combination: establishing a signal condition and indication in the peripheral subsystem of the given capability of a connected and controlling CPU, establishing and executing a short sequence of operations in said subsystem for a first capability controlling CPU including a sequence of responsive steps to a series of commands from such controlling CPU, and establishing and executing a long sequence of operations in said subsystem for a second capability controlling CPU, including sending a status signal in said long sequence to such second controlling CPU indicating an operational state in said interface detected by said subsystem, causing said second controlling CPU to initiate an action in said subsystem functionally equivalent of cooperative action in said short sequence between said first capability controlling CPU and the subsystem whereby the total operational capability of said second controlling CPU is effectively enhanced to that of said first controlling CPU.
Claim 11
Dependent Claim
211 words
The method set forth in claim 8 wherein said CPU capabilities relate to automatic recovery from error conditions in said subsystem; actuating a first controlling CPU to actuate said subsystem to perform a first short sequence including logging error conditions therein and sending a DISCONNECT IN signal to said first controlling CPU and then actuating said subsystem to await a command signal from such first controlling CPU; then actuating said first controlling CPU to sequence reset and sense short-sequence commands to said subsystem, actuating said subsystem to perform said short-sequence commands and then actuating said first controlling CPU to try a data processing operation with the subsystem; and actuating a second controlling CPU to actuate said subsystem upon detection of an error to log said error, then actuating said subsystem to perform said RESET as a said long sequence, actuating the subsystem to send to said second controlling CPU an error indicator indicating an error in said connections, actuating said second controlling CPU to attempt error recovery for such indicated error by sequencing a SENSE command followed by a data processing command, and actuating said subsystem to respond to such commands thereby emulating said second controlling system operation to said first controlling CPU operation with respect to such error recovery procedure.
Claim 12
Dependent Claim
23 words
The method set forth in claim 9 further actuating said subsystem to detect such errors during idle periods interleaved with data processing commands.
Claim 13
Dependent Claim
41 words
The method set forth in claim 10 further actuating said subsystem to prevent said connection error indication before initiating said RESET and during said RESET actuating the subsystem to set a busy status to prevent selection before subsystem reset is complete.
Claim 14
Dependent Claim
188 words
A two-mode I/O controller (CU) having a microprocessor, and signal processing circuits, said I/O controller adapted to be connected to either a first or second type controlling system, the improvement including the two-mode control in combination: control memory means containing control programs, each program having a routine starting address in the control memory, interface circuits in said controller adapted to be connected to either a first or second type controlling system, means indicating the type of system to which CU is connected, means supplying an indication of a given operational staTe in the controller, means indicating an error, ERRL means jointly responsive to one of said type indications indicating a second type controlling system and to said error indication to initiate a first action in said microprocessor and simultaneously indicate busy status, DIL means jointly responsive to said error condition and to another one of said type indications indicating said first type controlling system to supply an error indication, and means in said interface circuits responsive to certain received signal for initiating said first action and including means combining said EERL means initiation with said received signal initiation.
Claim 15
Dependent Claim
188 words
A two-mode I/O controller (CU) having a microprocessor, and signal processing circuits, said I/O controller adapted to be connected to either a first or second type controlling system, the improvement including the two-mode control in combination: control memory means containing control programs, each program having a routine starting address in the control memory, interface circuits in said controller adapted to be connected to either a first or second type controlling system, means indicating the type of system to which CU is connected, means supplying an indication of a given operational staTe in the controller, means indicating an error, ERRL means jointly responsive to one of said type indications indicating a second type controlling system and to said error indication to initiate a first action in said microprocessor and simultaneously indicate busy status, DIL means jointly responsive to said error condition and to another one of said type indications indicating said first type controlling system to supply an error indication, and means in said interface circuits responsive to certain received signal for initiating said first action and including means combining said EERL means initiation with said received signal initiation.
Claim 16
Dependent Claim
124 words
The two-mode controller set forth in claim 12 wherein said circuit means includes: trap means responsive to said operational indication to trap said microprocessor to a given routine starting address irrespective of which type of controlling system is connected thereto, memory means for memorizing said operational indication only when said second controlling system is connected to said interface circuits, forcing means responsive to said memory means for establishing an operation in said microprocessor settable by said first controlling system in response to a signal representing said operational condition, and said microprocessor responsive to said given operational state to indicate an error condition recoverable by said second controlling system even though said operational indication relates to an error not recoverable by such second controlling system.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-03-19 | 1976-09-18 | 1977-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-03-19 | 1980-09-18 | 1981-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-03-19 | 1984-09-18 | 1985-03-20 | $7700.00 | Window Closed / Lapsed |