US3711829A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Receiver for data transmission
Assignee: Alcatel CIT SA
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Filing: 1971-10-13
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Granted: 1973-01-16
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Expires: 1991-10-13
Abstract
Abstract A device which improves the process of identification of the characters of erroneous data resulting from disturbances in the transmission which includes the evaluation of two successive characters and the determination that both characters are accurate before the first of the two characters will be transferred to the output device.
Inventors
- 👤 C Lubrano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:35
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
173 words
A receiver for the transmission of multi-bit characters of data each including information bits and at least one redundancy bit providing for improved protection against errors comprising input storage means for storing all of the bits of one character at a time, logic circuit means for evaluating the accuracy of the bits stored in said input register means and generating a transfer signal when the character is found to be accurate, a load device operative in response to receipt of the information bits of a character of data, buffer storage means for storing all of the information bits of one character at a time, first transfer means responsive to said transfer signal of said logic circuit means for transferring the information bits from said input storage means to said buffer storage means, second transfer means for transferring the information bits in said buffer storage means to said load device, and control means responsive to said logic circuit means for actuating said second transfer means only upon receipt of two transfer signals in Succession.
Claim 2
Dependent Claim
173 words
A receiver for the transmission of multi-bit characters of data each including information bits and at least one redundancy bit providing for improved protection against errors comprising input storage means for storing all of the bits of one character at a time, logic circuit means for evaluating the accuracy of the bits stored in said input register means and generating a transfer signal when the character is found to be accurate, a load device operative in response to receipt of the information bits of a character of data, buffer storage means for storing all of the information bits of one character at a time, first transfer means responsive to said transfer signal of said logic circuit means for transferring the information bits from said input storage means to said buffer storage means, second transfer means for transferring the information bits in said buffer storage means to said load device, and control means responsive to said logic circuit means for actuating said second transfer means only upon receipt of two transfer signals in Succession.
Claim 3
Dependent Claim
21 words
A receiver as defined in claim 1 further including acceptance means responsive to said control means for generating an acceptance signal.
Claim 4
Dependent Claim
65 words
A receiver as defined in claim 2 wherein said control means includes a storage element connected to the output of said logic circuit means and an AND gate having one input connected to the output of said logic circuit means and a second input connected to said storage element, the output of said AND gate being connected to said second transfer means in control thereof.
Claim 5
Dependent Claim
48 words
A receiver as defined in claim 3 wherein said control means further includes resetting means responsive to absence of a transfer signal at the output of said logic circuit means at the end of the transmission of a character for clearing said acceptance means and said storage element.
Claim 6
Dependent Claim
27 words
A receiver as defined in claim 4 wherein said storage element is a flip-flop having its control input connected to the output of said logic circuit means.
Claim 7
Dependent Claim
27 words
A receiver as defined in claim 5 wherein said acceptance means is an additional flip-flop having its control input connected to the output of said AND gate.
Claim 8
Dependent Claim
65 words
A receiver as defined in claim 1 wherein said control means includes a storage element connected to the output of said logic circuit means and an AND gate having one input connected to the output of said logic circuit means and a second input connected to said storage element, the output of said AND gate being connected to said second transfer means in control thereof.
Claim 9
Dependent Claim
27 words
A receiver as defined in claim 7 wherein said storage element is a flip-flop having its control input connected to the output of said logic circuit means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-01-16 | 1976-07-17 | 1977-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-01-16 | 1980-07-17 | 1981-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-01-16 | 1984-07-17 | 1985-01-16 | $7700.00 | Window Closed / Lapsed |