Binary synchronous up/down counter

Claim 2

In a counter circuit, at least one four bit adder circuit having a plurality of control input terminals, four bit input terminals, a carry-in input terminal, for sum ( Sigma ) output terminals and at least one carry-out terminal, four flip-flop circuits, each of which flip-flop circuits includes at least one input terminal and at least one output terminal, first means connecting the output terminal of each of said four flip-flop circuits to a correspondingly different one of said four bit input terminals on said adder circuit to provide the count on said output terminals of said flip-flop circuits to the four bit input terminals of said adder circuit, second means connecting the input terminal of each of said four flip-flop circuits to a correspondingly different one of said sum ( Sigma ) adder output terminals to provide the total output of said adder circuit to said flip-flop circuits, control means for connecting control signals to said adder control input terminals and said carry-in input for combining with the count on said adder input terminals as received from said flip-flop circuits, and means for providing clock pulses to said flip-flop circuits to control same to reGister the total count which appears on said adder output terminals and thereby correspondingly change the count applied to said adder input terminals.

Claim 3

A control circuit as set forth in claim 1 which includes adjustable means for providing different marking signals to said control input terminals to thereby vary the count operation of the counter circuit.

Claim 4

A counter circuit as set forth in claim 1 in which said control input terminals are the B inputs of an adder circuit and said bit input terminals are the A inputs of an adder circuit.

Claim 5

A counter circuit as set forth in claim 1 which includes means for marking said control input terminals to provide a down count with the provision of each clock pulse to said flip-flop circuits.

Claim 6

A counter circuit as set forth in claim 1 which includes means for marking said control input terminals to provide a count increase with the provision of each clock pulse to said flip-flop circuits.

Claim 7

A counter circuit as set forth in claim 1 in which said count flip-flop includes a set terminal, and an input circuit over which logic 1 and logic 0 signals are applied to said flip-flop circuits to load a count therein.

Claim 8

A counter circuit as set forth in claim 1 in which said means for providing clock pulses to said flip-flop circuits includes a start-stop control circuit for stopping said counter after a predetermined number of counts.

Claim 9

A counter circuit as set forth in claim 1 in which an adder and its interconnect flip-flops comprise one stage, and in which said counter circuit includes a plurality of said stages, and means connecting the carry out terminal of each stage in the counter to the carry in input terminal of a different stage.

Claim 10

In a counter circuit, at least one n bit adder circuit having a first plurality of input terminals, a second plurality of input terminals, a carry-in terminal, a plurality of sum ( Sigma ) output terminals and a carry-out terminal, a plurality of flip-flop circuits, each of which flip-flop circuits includes at least one input terminal and at least one output terminal, first means connecting the output terminal of each of said flip-flop circuits to a correspondingly different one of said second plurality of input terminals on said adder circuit to provide the count on said output terminals of said flip-flop circuits to the second plurality of input terminals of said adder circuit, second means connecting the input terminal of each of said flip-flop circuits to a correspondingly different one of said sum ( Sigma ) output terminals to provide the total output of said adder circuit to said flip-flop circuits, control means for connecting control signals to said first plurality of input terminals of said adder circuit for combining with the count on said adder input terminals as received from said flip-flop circuits, and means for providing lock pulses to said flip-flop circuits to control same to register the total count which appears on said adder output terminals and thereby correspondingly change the count applied to said adder input terminals.

Claim 11

In a counter circuit, at least one n bit adder circuit having a first plurality of input terminals, a second plurality of input terminals, a carry-in terminal, a plurality of sum ( Sigma ) output terminals and a carry-out terminal, a plurality of flip-flop circuits, each of which flip-flop circuits includes at least one input terminal and at least one output terminal, first means connecting the output terminal of each of said flip-flop circuits to a correspondingly different one of said second plurality of input terminals on said adder circuit to provide the count on said output terminals of said flip-flop circuits to the second plurality of input terminals of said adder circuit, second means connecting the input terminal of each of said flip-flop circuits to a correspondingly different one of said sum ( Sigma ) output terminals to provide the total output of said adder circuit to said flip-flop circuits, control means for connecting control signals to said first plurality of input terminals of said adder circuit for combining with the count on said adder input terminals as received from said flip-flop circuits, and means for providing lock pulses to said flip-flop circuits to control same to register the total count which appears on said adder output terminals and thereby correspondingly change the count applied to said adder input terminals.

Claim 12

A counter circuit as set forth in claim 9 in which said control means includes adjustable means for providing different potential markings on said first plurality of input terminals to thereby vary the operation of the counter circuit.

Claim 13

A control circuit as set forth in claim 9 which includes means operative to mark said first plurality of input terminals of said adder circuit to provide a predetermined down count with each input to said second plurality of input terminals by said flip-flop circuits.

Claim 14

A counter circuit as set forth in claim 9 in which each flip-flop circuit includes a set terminal input, and in which said counter circuit includes means for simultaneously setting the flip-flop circuits to a set condition which represent a desired start count.

Claim 15

A system as set forth in claim 12 which includes an output circuit, and in which said means for providing clock pulses to said flip-flop cIrcuits includes delay means connected between said carry out terminal and said output circuit.

Claim 16

A system as set forth in claim 9 in which said means for connecting clock pulses to said flip-flop circuits includes gate means, and which includes means for controlling said gate means to terminate said clock pulses to said flip-flops responsive to operation of said flip-flops to a predetermined count.

Claim 17

A system as set forth in claim 14 in which said gate means includes a plurality of terminals, and in which said last means includes a connection from said carry out to one of said input terminals on said gate means.

Claim 18

A system as set forth in claim 9 in which said means for providing clock pulses to said flip-flops comprise a free running oscillator.

Claim 19

A system as set forth in claim 9 which includes means for connecting potentials to said first plurality of input terminals to effect jumping of the count to a value other than indicated by the input from said flip-flop circuits.

Claim 20

A system as set forth in claim 9 which includes means for providing potential signals to said first plurality of inputs to effect change of each count input from said flip-flops by a value other than one.

Claim 21

A counter circuit as set forth in claim 9 in which one n bit adder and said plurality of flip-flops connected thereto comprises one stage of the counter circuit, and which include means connecting the carry out terminal of each stage with the exception of the last stage to the carry in terminal of a different stage in the counter circuit.

Claim 22

A counter circuit as set forth in claim 9 in which the number of flip-flop circuits equals n, and which n 4.

Claim 23

A counter circuit as set forth in claim 9 in which the number of flip-flops which has its input and output terminals connected to its associated adder is less than n.