Learning circuit

Claim 2

A learning circuit of the type adapted to converge on a desired digital voltage output comprising means for generating random binary input numbers, means for converting said binary input numbers into input currents, means for generating solution control override currents, means for generating feedback currents, means for summing said input current with said solution control override current and said feedback current to form a sum current, means responsive to the polarity of said sum current for generating an output voltage with the polarity of said output voltage dependent upon the polarity of said sum current, said means for generating a feedback current comprising a counter responsive to one polarity of said output voltage for counting up and to the opposite polarity of said output voltage for counting down, said counter having a predetermined range with upper and lower limits and having a binary counter state output, and means responsive to said binary counter state output for generating said input current whereby said counter converges on its upper or lower range so that said sum current and hence said voltage converges on one polarity.

Claim 3

A learning circuit of the type adapted to converge on a desired digital voltage circuit output in response to solution control signals comprising: a random input generator for producing digital circuit input signals according to a predetermined probability distribution, a first digital to analog converter for converting said digital input signals to a discrete analog input current, a second digital to analog converter responsive to the solution control signal for producing discrete analog solution control currents, a digital counter having a digital voltage counting feedback and an output comprising a digital binary counter state feedback signal, a third digital to analog converter for converting said counter state feedback signal to a discrete analog feedback current, a current node for summing said input current, said solution control current and said feedback current, said current node having a sum current output, and an analog to digital converter responsive to the polarity of the sum current output for generating a digital voltage circuit output, said digital voltage circuit output also being applied to said digital voltage counting input of said digital counter.

Claim 4

A learning circuit of the type adapted to converge on a desired digital voltage circuit output in response to solution control signals comprising: a random input generator for producing digital circuit input signals according to a predetermined probability distribution, a first digital to analog converter for converting said digital input signals to a discrete analog input current, a second digital to analog converter responsive to the solution control signal for producing discrete analog solution control currents, a digital counter having a digital voltage counting feedback and an output comprising a digital binary counter state feedback signal, a third digital to analog converter for converting said counter state feedback signal to a discrete analog feedback current, a current node for summing said input current, said solution control current and said feedback current, said current node having a sum current output, and an analog to digital converter responsive to the polarity of the sum current output for generating a digital voltage circuit output, said digital voltage circuit output also being applied to said digital voltage counting input of said digital counter.

Claim 5

A learning circuit in accordance with claim 2 in which said digital counter counts up one unit for each application of a counting input of one polarity and counts down one unit for each application of a counting input of an opposite polarity.

Claim 6

A learning circuit in accordance with claim 3 in which said counter has a defined counter state range having upper and lower limits and wherein said counter converges on one of said upper and lower limits whereby additional counting inputs of said one polarity cease to affect said counter when said counter is at said upper limit and wherein counting inputs of said opposite polarity cease to affect said counter when said counter is at said lower limit.

Claim 7

A learning circuit in accordance with claim 2 in which said input signals to said first, second and third digital to analog converters are binary inputs each having multiple digits and wherein said first, second and third digital to analog converters each comprise a transistor having a base electrode, a collector electrode and multiple emitter electrodes, means for providing a fixed bias at said base electrode, each of said multiple emitter electrodes connected in series with a resistor having a predetermined value, the predetermined values of said resistor being related to each other according to powers of 2, said binary input having each of its digits respectively coupled to one of said multiple emitter electrodes with each of said binary digits operating to provide emitter biasing for enabling the emitter to which it is coupled whereby current is conducted through enabled emitters with the sum of the emitter currents and hence the collector current being a discrete current proportional to the binary number inputs.

Claim 8

A learning circuit in accordance with claim 2 wherein said random input generator is of the type adapted to produce binary signals corresponding to the numbers 2, 4, 6, 8, 10, 12 and 14, in accordance with a Gaussian occurrence probability with 8 being the median occurrence.

Claim 9

A learning circuit in accordance with claim 2 wherein said first, second and third digital to analog converters comprise current generators producing discrete analog output currents in response to binary inputs and wherein a current level of 0 corresponds to a binary input of 8 with binary inputs greater than 8 generating proportional levels of sourcing current and binary inputs of less than 8 generating proportional levels of sinking current.

Claim 10

A learning circuit in accordance with claim 2 wherein said second digital to analog converter is responsive to a solution control input of one polarity for generating a sourcing current larger than either said input current or said feedback current and responsive to a solution control input of an opposite polarity for generating a sinking current larger than either said input current or said feedback current.

Claim 11

A learning circuit of the type adapted to converge on a desired digital voltage output in response to reward and punishment signals comprising: a random input generator for producing digital circuit input signals according to a predetermined probability distribution, a first digital to analog converter for converting said digital input signals to discrete analog input currents, a second digital to analog converter responsive to the reward and punishment signals for producing reward and punishment currents, a digital counter having a digital voltage counting input and an output comprising a digital binary counter state feedback signal, a third digital to analog converter for converting said counter state feedback signal to a discrete analog feedback current, a current node for summing said input current with said reward and punishment current and said feedback current to form a sum current output, an analog to digital converter responsive to the polarity of said sum current output for generating a digital voltage output with the polarity of said voltage output corresponding to the polarity of said sum current output, said voltage output being applied to said digital voltage counting input of said digital counter, reward means comprising a unit amplifier actuated by a reward signal for coupling said voltage output to said second digital to analog converter, punishment means comprising a unit inverter actuated by a punishment signal for coupling the inverse of said voltage output to said second digital to analog converter, said second digital to analog converter responsive to said reward means for generating a reward current tending to increase the magnitude of said sum current output and responsive to said punishment means for generating a punishment current tending to decrease the magnitude of said sum current output.

Claim 12

A learning circuit of the type adapted to converge on a desired digital voltage output in response to reward and punishment signals comprising: a random input generator for producing digital circuit input signals according to a predetermined probability distribution, a first digital to analog converter for converting said digital input signals to discrete analog input currents, a second digital to analog converter responsive to the reward and punishment signals for producing reward and punishment currents, a digital counter having a digital voltage counting input and an output comprising a digital binary counter state feedback signal, a third digital to analog converter for converting said counter state feedback signal to a discrete analog feedback current, a current node for summing said input current with said reward and punishment current and said feedback current to form a sum current output, an analog to digital converter responsive to the polarity of said sum current output for generating a digital voltage output with the polarity of said voltage output corresponding to the polarity of said sum current output, said voltage output being applied to said digital voltage counting input of said digital counter, reward means comprising a unit amplifier actuated by a reward signal for coupling said voltage output to said second digital to analog converter, punishment means comprising a unit inverter actuated by a punishment signal for coupling the inverse of said voltage output to said second digital to analog converter, said second digital to analog converter responsive to said reward means for generating a reward current tending to increase the magnitude of said sum current output and responsive to said punishment means for generating a punishment current tending to decrease the magnitude of said sum current output.

Claim 13

A learning circuit in accordance with claim 9 wherein said second digital to analog converter has a preset input, said second digital to analog converter responsive to said preset input for generating a preset current which is summed with said input current and said feedback current by said current node and said preset current overriding said input current and feedback current to initially control the polarity of said sum current output and hence the polarity of said voltage output.