US3701027A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital frequency synthesizer
Assignee: Bunker Ramo Corp
•
Filing: 1971-04-15
•
Granted: 1972-10-24
•
Expires: 1991-04-15
Abstract
Abstract A circuit for simultaneously generating a plurality of signals at related frequencies. A clock source, the frequency of which is greater than the frequency of any of the signals to be generated, is applied to the input to a scaler circuit. The scaler circuit generates a plurality of output signals, there being an output signal from the scaler circuit corresponding to each of the related frequency signals to be generated. At least some of the signals from the scaler have non-uniform pulse-to-pulse spacing. The outputs from the scaler circuit are then converted into signals at the desired frequencies with substantially uniform pulse-to-pulse spacing. For the preferred embodiment of the invention, this is accomplished by scaling the signals from the scaler circuit at frequencies which are multiples of the corresponding signals of related frequencies and then dividing down each signal from the scaler to obtain the desired signals.
Inventors
- 👤 John Price Belton Jr
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:29
CPC Classifications
A; A61; A61B; A61B5/00; A61B5/12; A61B5/121; G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; H; H03; H03B; H03B21/00; H03B21/01; H03B21/02; H03B21/025
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
197 words
A circuit for simultaneously generating a plurality of pulse signals at different frequencies comprising: a clock signal source, the frequency of said clock signal source being greater than the frequency of any of said different frequencies; scaler means for converting said clock signal into a plurality of pulse trains each of which is at a frequency which is a multiple of one of said different frequencies and at least some of the signals from said scaler means having non-uniform pulseto-pulse spacing; said scaler means including a multistage synchronous counter, and gating means responsive to output pulses from selected one or more stages of said counter for generating at least one of the pulse trains from said scaler; and dividing means for dividing down the signals from said scaler means to generate signals at said different frequencies; the frequency of said clock signal source being chosen sufficiently high so that the pulse trains provided by said scaler means have frequencies which permit the pulse trains to be divided down by said dividing means by an amount sufficient to cause the resulting output signals at said different frequencies generated by said dividing means to have substantially uniform pulse-to-pulse spacing.
Claim 2
Dependent Claim
197 words
A circuit for simultaneously generating a plurality of pulse signals at different frequencies comprising: a clock signal source, the frequency of said clock signal source being greater than the frequency of any of said different frequencies; scaler means for converting said clock signal into a plurality of pulse trains each of which is at a frequency which is a multiple of one of said different frequencies and at least some of the signals from said scaler means having non-uniform pulseto-pulse spacing; said scaler means including a multistage synchronous counter, and gating means responsive to output pulses from selected one or more stages of said counter for generating at least one of the pulse trains from said scaler; and dividing means for dividing down the signals from said scaler means to generate signals at said different frequencies; the frequency of said clock signal source being chosen sufficiently high so that the pulse trains provided by said scaler means have frequencies which permit the pulse trains to be divided down by said dividing means by an amount sufficient to cause the resulting output signals at said different frequencies generated by said dividing means to have substantially uniform pulse-to-pulse spacing.
Claim 3
Dependent Claim
16 words
A circuit of the type described in claim 1 wherein said different frequencies are harmonically related.
Claim 4
Dependent Claim
47 words
A circuit of the type described in claim 1 wherein said dividing means includes a multistage synchronous counter for each signal from said scaler which is to be divided down, the output from the last stage of said counter being one of said signals of different frequency.
Claim 5
Dependent Claim
42 words
A circuit of the type described in claim 3 wherein the number of stages of the counter of said dividing means is equal to N where 2N is the quantity by which the signal from said scaler is to be divided down.
Claim 6
Dependent Claim
37 words
A circuit of the type described in claim 1 wherein said scaler has a single synchronous counter and wherein said gating means includes a separate gating means for each of said plurality of signals from said scaler.
Claim 7
Dependent Claim
24 words
A circuit of the type described in claim 1 including means for converting the plurality of pulse signals into a plurality of sine-wave signals.
Claim 8
Dependent Claim
39 words
A circuit of the type described in claim 1 wherein the frequency of said clock signal is M times the frequency of the highest frequency signal to be generated, where M is the divide ratio of said dividing means.
References Cited (Backward Citations)
US2994790A
Cited
US3023363A
Cited
US3241038A
Cited
US3172042A
Cited
US3430067A
Cited
US3403343A
Cited
US3493872A
Cited
US3543295A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-24 | 1976-04-24 | 1976-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-24 | 1980-04-24 | 1980-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-24 | 1984-04-24 | 1984-10-24 | $7700.00 | Window Closed / Lapsed |