Memory system including buffer memories

Claim 2

A buffer memory system, comprising an address register for set bits and tag bits, a main memory having information block storage locations addressable by said set and tag bits in combination, a buffer memory having storage locations addressable by said set bits for the storage of tags and associated information blocks, means utilizing the contents of said address register to transfer an addressed information block from said main memory and a corresponding tag from said address register to a location in said buffer memory determined by the set bits in said address register, a content-addressed memory for the storage of associated tags, sets and information blocks, and means to transfer an information block and associated tag bits from said buffer memory together with set bits from said address register to said content-addressed memory.

Claim 3

A buffer memory system, comprising an address register for set bits and tag bits, a main memory having information block storage locations addressable by said set and tag bits in combination, two buffer memory banks each having storage locations addressable by said set bits for the storage of tags and associated information blocks, means utilizing the contents of said address register to transfer an addressed information block from said main memory and a corresponding tag from said address register to a buffer memory bank at a location determined by the set bits in said address register, a content-addressed memory for the storage of associated tags, sets and information blocks, and means to transfer an information block and associated tag bits from a buffer memory bank together with set bits from said address register to said content-addressed memory.

Claim 4

A buffer memory system, comprising an address register for set bits and tag bits, a main memory having information block storage locations addressable by said set and tag bits in combination, two buffer memory banks each having storage locations addressable by said set bits for the storage of tags and associated information blocks, means utilizing the contents of said address register to transfer an addressed information block from said main memory and a corresponding tag from said address register to a buffer memory bank at a location determined by the set bits in said address register, a content-addressed memory for the storage of associated tags, sets and information blocks, and means to transfer an information block and associated tag bits from a buffer memory bank together with set bits from said address register to said content-addressed memory.

Claim 5

A system as defined in claim 2, wherein each of said two memory banks has storage locations for one information block belonging to each of the sets of information blocks.

Claim 6

A system as defined in claim 3, and in addition, a bank selection logic unit for selectively directing an information block to one of the two banks.

Claim 7

A system as defined in claim 4 wherein each said memory bank is constructed so that a tag and information block displaced from a storage location therein is transferred to said content-addressed memory.

Claim 8

A system as defined in claim 5, and in addition, means to determine whether a desired information block is present in any of said memory banks and said content-addressed memory, and means conditioned thereby to read out the desired information block therefrom.

Claim 9

A system as defined in claim 4, and in addition, means responsive to the absence of a desired information block in any of said memory banks and said content-addressed memory to thereupon read out the desired information block from said main memory.

Claim 10

A buffer memory system, comprising an address register having a set portion for set bits and having a tag portion for tag bits, a main memory having information block storage locations addressable by said set and tag bits in combination, at least two buffer memory banks each having storage locations addressable by said set bits for the storage of tags and associated information blocks, a content addressed memory for the storage of associated tags, sets, and information blocks, means to determine whether an information block corresponding to the contents of the set and tag portions of said address register is present in one of said buffer memory banks or said content addressed memory, and to provide ''''present'''' and ''''not present'''' output signals, means responsive to a ''''present'''' signal to read out the corresponding information block, means responsive to ''''not presnent'''' signals to apply the set and tag bits to the main memory to read out the corresponding information block, and which includes means to transfer the tag portion of the address and the information block to a location determined by the set portion of said address into one of said buffer memory banks, and means operative when a tag and information block are applied to an already occupied location in a buffer memory bank to transfer the displaced tag and information block together with the set portion of the address to said content addressed memory, whereby said content addressed memory provides rapid-access storage space for additional information blocks belonging to the same sets as information blocks stored in the two buffer memory banks.

Claim 11

A buffer memory system, comprising an address register having a set portion for set bits and having a tag portion for tag bits, a main memory having information block storage locations addressable by said set and tag bits in combination, at least two buffer memory banks each having storage locations addressable by said set bits for the storage of tags and associated information blocks, a content addressed memory for the storage of associated tags, sets, and information blocks, means to determine whether an information block corresponding to the contents of the set and tag portions of said address register is present in one of said buffer memory banks or said content addressed memory, and to provide ''''present'''' and ''''not present'''' output signals, means responsive to a ''''present'''' signal to read out the corresponding information block, means responsive to ''''not presnent'''' signals to apply the set and tag bits to the main memory to read out the corresponding information block, and which includes means to transfer the tag portion of the address and the information block to a location determined by the set portion of said address into one of said buffer memory banks, and means operative when a tag and information block are applied to an already occupied location in a buffer memory bank to transfer the displaced tag and information block together with the set portion of the address to said content addressed memory, whereby said content addressed memory provides rapid-access storage space for additional information blocks belonging to the same sets as information blocks stored in the two buffer memory banks.