US3699532A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiprogramming control for a data handling system
Assignee: Singer Co
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Filing: 1970-04-27
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Granted: 1972-10-17
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Expires: 1990-04-27
Abstract
Abstract A data handling system including a plurality of groups of data originating and/or receiving devices operable asynchronously and independently with respect to each other, each group of such devices being coupled with an associated data transmission controller by means of a common data channel for buffering one unit (character) of data and providing certain basic data transmission controls for transmission of a character between an associated device and a common input/output data channel extending between the controllers and a supervisory control unit which is coupled with a main memory unit and a second data transmission channel. The second data transmission channel provides for transmission of characters between the supervisory control unit, the main memory unit and a data bank comprising a plurality of data storage or secondary data handling devices. The supervisory control unit provides the necessary elementary functional components to handle and control transmission of data between the data input/output devices and, the main memory and the data bank. The main memory unit is partitioned into a plurality of a section by means of adjustable hardware connected at each data transmission controller so as to permit only the data originating/receiving devices associated with it to communicate with an associated particular partitioned section of memory and an additional section of the memory is provided that is accessible to all partitions of the main memory unit. The supervisory control unit provides for a program stored in each particular section of the main memory unit to be executed for a predetermined period of time and then upon completion of successful branch operation in the program for a switch to performance of the program in the next section in a continuous round robbin for all sections manner. When a program instruction in one section of the main memory unit dictates performance of input/output operation a switch is made to another section but processing is suspended until the input/output operation is completed and then processing is commenced of the program instructions in the next section of the main memory unit. The supervisory control unit also includes functional components to perform certain basic arithmetic operations on the various data such as addition, subtraction, etc.
Inventors
- 👤 Harry G Schaffer
- 👤 Dan A Neilson
- 👤 Eleuthere Poumakis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:31
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F9/4825; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06Q; G06Q10/00; G06Q10/08; G06Q10/087; H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
338 words
In a multiprogramming data processing system wherein a plurality of addressable input/output devices originate and receive data asynchronously with respect to each other and are segregable into separate groups, the combination which comprises: an input/ouput controlling device connected to at least one such input/output device for controlling the transmission of data to or receipt of data from such a device, said controlling device further including means to generate an interrupt signal in response to an associated input/output device desiring to transmit or to receive data; a main memory unit coupled to each input/output controlling device and partitioned into a plurality of sequentially ordered sections which receive data and instruction words in the form of a program in each section, the number of sections being at least as great as the number of input/output controlling devices and with each section of the memory being associated with and accessible to only one particular controlling device; control means coupled to the input/output controlling devices and to the main memory unit and responsive to the program contained in each section of the memory to execute the program instructions for a predetermined time period, said control means including means responsive to the end of said time period and to the completion of a successful branch instruction of that program to suspend execution of that program and to similarly commence execution of the program instructions contained in the next sequentially ordered section of memory with the execution of the programs in all sections of the memory continuing in a sequential round robbin manner; and means responsive to an interrupt signal received from an input/output controlling device to suspend execution of a program in a section of the main memory unit and to direct performance of the input/output command from the controlling device and any other input/output commands from any other controlling devices, said means further including means responsive to the completion of performance of said input/ouput commands to direct execution of the program contained in the next sequential section of the main memory unit.
Claim 2
Dependent Claim
338 words
In a multiprogramming data processing system wherein a plurality of addressable input/output devices originate and receive data asynchronously with respect to each other and are segregable into separate groups, the combination which comprises: an input/ouput controlling device connected to at least one such input/output device for controlling the transmission of data to or receipt of data from such a device, said controlling device further including means to generate an interrupt signal in response to an associated input/output device desiring to transmit or to receive data; a main memory unit coupled to each input/output controlling device and partitioned into a plurality of sequentially ordered sections which receive data and instruction words in the form of a program in each section, the number of sections being at least as great as the number of input/output controlling devices and with each section of the memory being associated with and accessible to only one particular controlling device; control means coupled to the input/output controlling devices and to the main memory unit and responsive to the program contained in each section of the memory to execute the program instructions for a predetermined time period, said control means including means responsive to the end of said time period and to the completion of a successful branch instruction of that program to suspend execution of that program and to similarly commence execution of the program instructions contained in the next sequentially ordered section of memory with the execution of the programs in all sections of the memory continuing in a sequential round robbin manner; and means responsive to an interrupt signal received from an input/output controlling device to suspend execution of a program in a section of the main memory unit and to direct performance of the input/output command from the controlling device and any other input/output commands from any other controlling devices, said means further including means responsive to the completion of performance of said input/ouput commands to direct execution of the program contained in the next sequential section of the main memory unit.
Claim 3
Dependent Claim
43 words
The system described in claim 1 wherein: the partitioning of the main memory unit into sections is provided by adjustable connections on each input/output controlling device which determine the portion of the main memory unit that is accessible by that particular controlling device.
Claim 4
Dependent Claim
45 words
The system described in claim 2 further including: additional memory modules which are similar to the original main memory unit, to be similarly coupled to the control means and to the input/output controlling devices, whereby the storage capacity of the original main memory is expanded.
Claim 5
Dependent Claim
70 words
The system described in claim 1 wherein: the main memory unit contains a section in addition to those sections associated with individual controlling devices, which additional section contains a portion in which data and program instructions may be retrievably inserted from other sections and also contains a privileged section from which other sections can read data or program instructions but into which the sections cannot insert data or program instructions.
Claim 6
Dependent Claim
39 words
The system described in claim 3 wherein: a secondary mass memory storage bank is coupled to the main memory unit and is adapted to provide additional data storage for the main memory unit and to the input-output controlling devices.
Claim 7
Dependent Claim
41 words
The system described in claim 5 wherein: the secondary mass memory bank is coupled to the main memory unit and to the supervisory control unit by means which restrict the access to the memory bank to certain predetermined input/output controlling devices.
Claim 8
Dependent Claim
32 words
The system described in claim 1 wherein each input/output controlling device has an input/output device coupled to it by a two wire data bus over which the data transmission is bit-serial character-serial.
Claim 9
Dependent Claim
393 words
A multiprogramming data processing system which comprises: a plurality of addressable input/output devices, each of which is utilized to originate and receive data asynchronously with respect to each other and to transmit an interrupt signal when it requests to receive data or to transmit data and program instructions, said devices to be interconnected in predetermined groups; a plurality of controlling devices, each of which is coupled to at least one input/output device; a main memory coupled to the controlling devices for receiving and storing data and program instructions therefrom, said memory being sectioned into individual sequential portions, the number of which is at least equal to the number of controlling devices, each individual memory portion being associated with and accessible to only one controlling device; control means coupled to the main memory and to each controlling device, the control means executing the program instructions of a program stored in an individual portion of the main memory for a predetermined time, said control means responsive to the end of the predetermined time and to the occurreNce of a successful branch instruction to suspend execution of that particular program at that point and to switch to execution of the program instructions in the next sequential portion of the main memory for a similar execution of the program contained in that portion of the memory, the sequential switching of the execution of programs in individual portions of the memory continuing on a sequential and round robbin basis for all portions of the memory; and means responsive to an interrupt signal received from an input/output device via an individual controlling device to suspend the execution of a program instruction in an individual portion of the memory and to perform an input/output command for that controlling device, said means responsive to the completion of an input/output operation for that particular controlling device to check in sequence every other controlling device and to perform an input/output operation for each succeeding controlling device which has an outstanding input/output command, said means further including means responsive to the completion of performance of all input/output operations for the controlling devices to direct said control means to commence the performance of program instructions contained in the memory portion next in sequential order to the memory portion which had had its program instructions being executed at the time of response to the interrupt signal.
Claim 10
Dependent Claim
393 words
A multiprogramming data processing system which comprises: a plurality of addressable input/output devices, each of which is utilized to originate and receive data asynchronously with respect to each other and to transmit an interrupt signal when it requests to receive data or to transmit data and program instructions, said devices to be interconnected in predetermined groups; a plurality of controlling devices, each of which is coupled to at least one input/output device; a main memory coupled to the controlling devices for receiving and storing data and program instructions therefrom, said memory being sectioned into individual sequential portions, the number of which is at least equal to the number of controlling devices, each individual memory portion being associated with and accessible to only one controlling device; control means coupled to the main memory and to each controlling device, the control means executing the program instructions of a program stored in an individual portion of the main memory for a predetermined time, said control means responsive to the end of the predetermined time and to the occurreNce of a successful branch instruction to suspend execution of that particular program at that point and to switch to execution of the program instructions in the next sequential portion of the main memory for a similar execution of the program contained in that portion of the memory, the sequential switching of the execution of programs in individual portions of the memory continuing on a sequential and round robbin basis for all portions of the memory; and means responsive to an interrupt signal received from an input/output device via an individual controlling device to suspend the execution of a program instruction in an individual portion of the memory and to perform an input/output command for that controlling device, said means responsive to the completion of an input/output operation for that particular controlling device to check in sequence every other controlling device and to perform an input/output operation for each succeeding controlling device which has an outstanding input/output command, said means further including means responsive to the completion of performance of all input/output operations for the controlling devices to direct said control means to commence the performance of program instructions contained in the memory portion next in sequential order to the memory portion which had had its program instructions being executed at the time of response to the interrupt signal.
Claim 11
Dependent Claim
42 words
The system described in claim 8 wherein: the partitioning of the main memory unit into sections is provided by adjustable connections on each input/output controlling device which determine the portion of the main memory unit that is accessible by that particular device.
Claim 12
Dependent Claim
45 words
The system described in claim 9 further including: additional memory modules which are similar to the original main memory unit, to be similarly coupled to the control means and to the input/output controlling devices, whereby the storage capacity of the original main memory is expanded.
Claim 13
Dependent Claim
79 words
The system described in claim 8 wherein: the main memory unit contains a section in addition to those sections associated with individual controlling devices, which additional section contains a portion in which data and program instructions may be retrievably inserted from other sections and accessible thereto for reading only if so desired and also contains a privileged section from which other sections can read data or program instructions but into which the sections cannot insert data or program instructions.
Claim 14
Dependent Claim
36 words
The system described in claim 10 wherein: a secondary mass memory storage bank is coupled to the main memory unit for providing additional data storage for the main memory unit and to the input/output controlling devices.
Claim 15
Dependent Claim
41 words
The system described in claim 12 wherein: the secondary mass memory bank is coupled to the main memory unit and to the supervisory control unit by means which restrict the access to the memory bank to certain predetermined input/output controlling devices.
Claim 16
Dependent Claim
32 words
The system described in claim 8 wherein: each input/output controlling unit has an input/output device coupled to it by a two wire data bus over which the data transmission is bit-serial character-serial.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-10-17 | 1976-04-17 | 1976-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-10-17 | 1980-04-17 | 1980-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-10-17 | 1984-04-17 | 1984-10-17 | $7700.00 | Window Closed / Lapsed |