US3694760A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feedback switching circuit for eliminating error signals
Assignee: United States Department of the Navy
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Filing: 1970-09-30
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Granted: 1972-09-26
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Expires: 1990-09-30
Abstract
Abstract Apparatus for eliminating error currents normally prevalent when an associated operational amplifier is disconnected from its input source. A feedback arrangement comprising a field effect transistor switch in conjunction with a memory circuit reflects these error signals to the operational amplifier via a differential buffer amplifier, thereby causing said operational amplifier to null out the effects of the error currents.
Inventors
- 👤 Jack C Loessi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:34
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/38; H03F3/387; H03F3/393
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
397 words
Means for eliminating error signals, comprising: a first input terminal for receiving an input signal; a second input terminal connected to ground; an output terminal; amplifier circuit means having a feedback path arrangement: a first input for receiving said input signal from said first input terminal, said amplifier circuit means exhibiting error signals when said first input is not receiving said input signal; a second input for receiving said error signals from said feedback path arrangement, said amplifier circuit means thereupon eliminating the effect of said error signals; amplifier operation selection means connected in electrical parallelism across said amplifier circuit means, said amplifier operation Selection means determining the nature of the signal from said amplifier circuit means to be impressed upon said output terminal, memory circuit means connected in said feedback path arrangement with said amplifier circuit means, said memory circuit means reflecting said error signals to said second input of said amplifier circuit means, thereby causing said amplifier circuit means to eliminate the effect of said error signals; first and second bias potential sources; means for reflecting either said input signal or said error signal to said amplifier circuit means, said reflecting means comprising: a first field effect transistor comprising, a gate connected to said first input terminal, a source connected to said first bias potential source, and a drain connected to said first input of said amplifier circuit means, and a second field effect transistor comprising, a gate connected to the output of said memory circuit means, a source connected to said first bias potential source, and a drain connected to said second input of said amplifier circuit means, a first switching means connected intermediate said first and second input terminals and said gate of said first field effect transistor of said reflecting means, said first switching means applying either said input signal or ground potential to said gate of said first field effect transistor; and a second switching means connected intermediate said output terminal and said memory circuit means, said second switching means interrupting said feedback path arrangement when said first switching means is connected to said first input terminal, thereby allowing said input signal to be applied to said amplifier circuit means and completing said feedback path arrangement when said first switching means is connected to said second input terminal, thereby allowing said error signals to be applied to said amplifier circuit means.
Claim 2
Dependent Claim
397 words
Means for eliminating error signals, comprising: a first input terminal for receiving an input signal; a second input terminal connected to ground; an output terminal; amplifier circuit means having a feedback path arrangement: a first input for receiving said input signal from said first input terminal, said amplifier circuit means exhibiting error signals when said first input is not receiving said input signal; a second input for receiving said error signals from said feedback path arrangement, said amplifier circuit means thereupon eliminating the effect of said error signals; amplifier operation selection means connected in electrical parallelism across said amplifier circuit means, said amplifier operation Selection means determining the nature of the signal from said amplifier circuit means to be impressed upon said output terminal, memory circuit means connected in said feedback path arrangement with said amplifier circuit means, said memory circuit means reflecting said error signals to said second input of said amplifier circuit means, thereby causing said amplifier circuit means to eliminate the effect of said error signals; first and second bias potential sources; means for reflecting either said input signal or said error signal to said amplifier circuit means, said reflecting means comprising: a first field effect transistor comprising, a gate connected to said first input terminal, a source connected to said first bias potential source, and a drain connected to said first input of said amplifier circuit means, and a second field effect transistor comprising, a gate connected to the output of said memory circuit means, a source connected to said first bias potential source, and a drain connected to said second input of said amplifier circuit means, a first switching means connected intermediate said first and second input terminals and said gate of said first field effect transistor of said reflecting means, said first switching means applying either said input signal or ground potential to said gate of said first field effect transistor; and a second switching means connected intermediate said output terminal and said memory circuit means, said second switching means interrupting said feedback path arrangement when said first switching means is connected to said first input terminal, thereby allowing said input signal to be applied to said amplifier circuit means and completing said feedback path arrangement when said first switching means is connected to said second input terminal, thereby allowing said error signals to be applied to said amplifier circuit means.
Claim 3
Dependent Claim
110 words
The invention recited in claim 1, wherein said first switching means comprises: a third field effect transistor comprising, a gate connected to said second gate bias source, a source connected to said first input terminal, and a drain connected to said gate of said first field effect transistor; and a fourth field effect transistor comprising: a gate connected to said second gate bias source, a source connected to said second input terminal, and a drain connected to said gate of said first field effect transistor whereby when one of said third or fourth field effect transistors is in a state of conduction the other is in a state of non-conduction.
Claim 4
Dependent Claim
78 words
The invention as recited in claim 2, wherein said second switching means is a fifth field effect transistor comprising a gate connected to said second gate bias source, a source connected intermediate said output terminal and the output of said operational amplifier and a drain connected to said gate of said second field effect transistor, said fifth field effect transistor being in a state of conduction whenever said fourth field effect transistor is in a state of conduction.
Claim 5
Dependent Claim
45 words
The invention as recited in claim 3 wherein said memory circuit means is a capacitor having a first plate connected intermediate said drain of said fifth field effect transistor and said gate of said second field effect transistor, and a second plate connected to ground.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-26 | 1976-03-27 | 1976-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-26 | 1980-03-27 | 1980-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-26 | 1984-03-27 | 1984-09-26 | $7700.00 | Window Closed / Lapsed |