Abstract A receiving system has two receivers, each including a squelch circuit arranged to give an output when the carrier level at demodulator of the receiver exceeds a threshold value. An alarm circuit has a first memory circuit settable by the simultaneous presence of squelch outputs from both receivers at any time during a transmission period, a second memory circuit settable by an output from the first memory circuit in the set condition, and a third memory circuit settable by the presence of a squelch output from either or both receivers during the transmission period. The setting signal is applied to the third memory circuit via a first delay means so arranged that the third memory circuit is not set unless the squelch signal persists for a period greater than the duration of transient interfering signals. The third memory circuit produces an output pulse when the setting signal is removed at the end of the transmission period. The output pulse is applied to a reset terminal of the second memory circuit, and to a reset terminal of the first memory circuit via a delay means adapted to provide a delay at least equal to the duration of the output pulse. The output pulse generated at the end of a transmission period is ineffective to reset the second memory circuit if the first memory circuit has been set during that transmission period, but is effective if the first memory circuit has not been set.
A receiving system comprising two receivers for the reception of an RF signal, each receiver including a squelch circuit arranged to give an output when the carrier level at the demodulator of the receiver exceeds a threshold value, an alarm circuit comprising a first memory circuit settable by the simultaneous presence of squelch outputs from both receivers at any time during a transmission period, a second memory circuit settable by an output from the first memory circuit in the set condition, a third memory circuit settable by the presence of a squelch output from either or both receivers during the transmission period, the setting signal being applied to the third memory circuit via first delay means so arranged that the third memory circuit is not set unless the squelch signal persists for a period greater than the duration of transient interfering signal, the third memory circuit being adapted to produce an output pulse when the setting signal is removed at the end of the transmission period, said output pulse being applied to a reset terminal of the second memory circuit, and being also applied to a reset terminal of the first memory circuit via second delay means adapted to provide a delay at least equal to the duration of the said output pulse, whereby the output pulse generated by the third memory circuit at the end of a transmission period is ineffective to reset the second memory circuit if the first memory circuit has been set during that transmission period but is effective if the first memory circuit has not been set.
Claim 2
Dependent Claim
262 words
A receiving system comprising two receivers for the reception of an RF signal, each receiver including a squelch circuit arranged to give an output when the carrier level at the demodulator of the receiver exceeds a threshold value, an alarm circuit comprising a first memory circuit settable by the simultaneous presence of squelch outputs from both receivers at any time during a transmission period, a second memory circuit settable by an output from the first memory circuit in the set condition, a third memory circuit settable by the presence of a squelch output from either or both receivers during the transmission period, the setting signal being applied to the third memory circuit via first delay means so arranged that the third memory circuit is not set unless the squelch signal persists for a period greater than the duration of transient interfering signal, the third memory circuit being adapted to produce an output pulse when the setting signal is removed at the end of the transmission period, said output pulse being applied to a reset terminal of the second memory circuit, and being also applied to a reset terminal of the first memory circuit via second delay means adapted to provide a delay at least equal to the duration of the said output pulse, whereby the output pulse generated by the third memory circuit at the end of a transmission period is ineffective to reset the second memory circuit if the first memory circuit has been set during that transmission period but is effective if the first memory circuit has not been set.