US3689332A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of producing semiconductor circuits with conductance paths
Assignee: Siemens AG
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Filing: 1970-10-13
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Granted: 1972-09-05
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Expires: 1990-10-13
Abstract
Abstract A METHOD OF PRODUCING INTERGRATED CIRCUITS WITH CONDUCTANCE PATHS WHEREIN AN ORIGINAL BODY IS FIRST PROVIDED WITH A METAL ADHESIVE LAYER, THEN WITH A LAYER WHICH, PREFERABLY ACTS AS A BARRIER AND, FINALLY, WITH A GOLD LAYER WHICH FORMS CONDUCTANCE PATHS. PRIOR TO DEPOSITING THE GOLD LAYER, A PROTECTIVE LAYER IS APPLIED WHICH IS THEN ETCHED OFF, WITH THE AID OF A MASKING LAYER, IN THE REGIONS PROVIDED FOR THE CONDUCTANCE PATHS. AFTER APPLICATION OF THE GOLD LAYER, THE MASKING LAYER AND THE PROTECTIVE LAYER ARE REMOVED OUTSIDE THE CONDUCTANCE PATHS. FINALLY, THE LAYER WHICH, PREFERABLY SERVES AS A BARRIER AND THE ADHESIVE LAYER, ARE REMOVED OUTSIDE THE CONDUCTANCE PATHS.
Inventors
- 👤 Manfred Dietrich
- 👤 Helmut Eger
- 👤 Eckart Neubert
- 👤 Wolfgang Kruger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:33
CPC Classifications
H; H10; H10P; H10P95/00; H10W; H10W74/00; H10W74/40; H10W74/43; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/945; Y10S438/948; Y10S438/95
Claims Analysis
Total Claims: 0
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References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-09-05 | 1976-03-06 | 1976-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-09-05 | 1980-03-06 | 1980-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-09-05 | 1984-03-06 | 1984-09-05 | $7700.00 | Window Closed / Lapsed |