US3686665A
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US
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Digital function generator
Assignee: Leeds and Northrup Co
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Filing: 1969-12-31
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Granted: 1972-08-22
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Expires: 1989-12-31
Abstract
Abstract A method and apparatus for converting substantially instantaneous values of a variable analog input to substantially instantaneous values of a variable digital output which is a nonlinear function of the variable analog input. A particular linear segment approximating that portion of a nonlinear function on which a particular instantaneous value of the analog input is located is identified by accumulating a corresponding digital count in a register in response to gated clock pulses during a first digitized cycle and the register is then cleared. Stored count modifiers corresponding to the slope and intercept of the identified linear segment are entered into the register and a count is accumulated in the register in response to gated clock pulses generated during a second digitizing cycle, the accumulated count being the substantially instantaneous value of the digital output representing desired engineering units.
Inventors
- 👤 Laurence F Elias
- 👤 James H Magee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:18
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; H03M1/52; H03M1/58
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
105 words
A system for producing a digital output as a function of an input variable comprising: register means accumulating digital counts at a substantially constant rate during an identification cycle and a readout cycle; means responsive to a digital count accumulated during said identification cycle for selecting two count modifiers from a plurality of different count modifiers to be entered into said register means; and means operable before, during, or after said readout cycle for entering said two count modifiers in said register means such that the digital count accumulated during said readout cycle is the digital output and the desired function of the input variable.
Claim 2
Independent Claim
105 words
A system for producing a digital output as a function of an input variable comprising: register means accumulating digital counts at a substantially constant rate during an identification cycle and a readout cycle; means responsive to a digital count accumulated during said identification cycle for selecting two count modifiers from a plurality of different count modifiers to be entered into said register means; and means operable before, during, or after said readout cycle for entering said two count modifiers in said register means such that the digital count accumulated during said readout cycle is the digital output and the desired function of the input variable.
Claim 3
Dependent Claim
38 words
The system of claim 1 wherein said register means comprises a single register for accumulating said digital counts and said means operable before, during, or after said readout cycle enters said two count modifiers in said single register.
Claim 4
Dependent Claim
53 words
The system of claim 1 wherein said register means comprises two registers for accumulating said digital counts, said means operable before, during, or after said readout cycle entering one of said count modifiers in one of said two registers and the other of said count modifiers in the other of said two registers.
Claim 5
Independent Claim
138 words
A system of the type including a dual slope analog-to-digital converter having two digital counting periods in each digitizing cycle for producing a digital output as a function of an analog input, the improvement comprising: register means accumulating digital counts during each of two digitizing cycles; means responsive to the digital count at the end of the first of said digitizing cycles for selecting at least one count modifier from a plurality of different count modifiers; means operable after said at least one count modifier has been identified for clearing said register means; and means operable before the end of the second of said digitizing cycles for entering said at least one count modifier in said register means such that the digital count accumulated at the end of the second of said digitizing cycles is the digital output.
Claim 6
Independent Claim
138 words
A system of the type including a dual slope analog-to-digital converter having two digital counting periods in each digitizing cycle for producing a digital output as a function of an analog input, the improvement comprising: register means accumulating digital counts during each of two digitizing cycles; means responsive to the digital count at the end of the first of said digitizing cycles for selecting at least one count modifier from a plurality of different count modifiers; means operable after said at least one count modifier has been identified for clearing said register means; and means operable before the end of the second of said digitizing cycles for entering said at least one count modifier in said register means such that the digital count accumulated at the end of the second of said digitizing cycles is the digital output.
Claim 7
Dependent Claim
131 words
The system of claim 4 wherein: said means responsive to said digital count at the end of said first of said digitizing cycles selects a count modifier corresponding to the approximate slope of a linear segment approximating the function at an instantaneous value of the analog input and selects a second count modifier corresponding to the intercept of said segment; and said means operable before the end of the second of said digitizing cycles enters said slope count modifier in said register means before the end of the first of said two counting periods in the second of said two digitizing cycles and enters said intercept count modifier in said register means after the end of the first of said two counting periods in the second of said two digitizing cycles.
Claim 8
Dependent Claim
74 words
The system of claim 5 wherein said means operable before the end of the second of said digitizing cycles enters said slope count modifier in said register means before the beginning of the first of said two counting periods in the second of said two digitizing cycles and enters said intercept counT modifier in said register means at the beginning of the second of said counting periods of the second of said digitizing cycles.
Claim 9
Independent Claim
219 words
A system of the type including a digital transducer having a digital counting period in each digitizing cycle for producing a digital output as a function of an input variable, the improvement comprising: first register means accumulating digital counts during each of two digitizing cycles; second register means accumulating digital counts during each of said two digitizing cycles; means responsive to a digital count accumulated in said second register means during the counting period of each of said digitizing cycles to terminate a digital count accumulating in said first register means during the counting period of each of said two digitizing cycles; means responsive to the digital count accumulated in said first register means at the end of the counting period of the first of said two digitizing cycles for selecting one count modifier to be entered into said first register means and another count modifier to be entered into said second register means; and means operable before the end of the second of said two digitizing cycles for entering said one count modifier in said first register means and said other count modifier in said other register means such that the digital count accumulated in said first register means at the end of the counting period of the second of said two digitizing cycles is the digital output.
Claim 10
Independent Claim
219 words
A system of the type including a digital transducer having a digital counting period in each digitizing cycle for producing a digital output as a function of an input variable, the improvement comprising: first register means accumulating digital counts during each of two digitizing cycles; second register means accumulating digital counts during each of said two digitizing cycles; means responsive to a digital count accumulated in said second register means during the counting period of each of said digitizing cycles to terminate a digital count accumulating in said first register means during the counting period of each of said two digitizing cycles; means responsive to the digital count accumulated in said first register means at the end of the counting period of the first of said two digitizing cycles for selecting one count modifier to be entered into said first register means and another count modifier to be entered into said second register means; and means operable before the end of the second of said two digitizing cycles for entering said one count modifier in said first register means and said other count modifier in said other register means such that the digital count accumulated in said first register means at the end of the counting period of the second of said two digitizing cycles is the digital output.
Claim 11
Dependent Claim
123 words
The system of claim 7 wherein said means responsive to said digital count at the end of the first of said two digitizing cycles selects said one count modifier corresponding to the approximate intercept of a linear segment approximating the function at an instantaneous value of the analog input and selects another count modifier to correspond to the approximate slope of said linear segment; and said means operable before the end of the second of said digitizing cycles enters said one count modifier in said first register means and said other count modifier in said second register means after the counting period of the first of said two digitizing cycles and before the counting period of the second of said two digitizing cycles.
Claim 12
Independent Claim
107 words
A system for generating a digital count as an output which is a function of an input variable comprising: register means for accumulating digital counts in response to the input during identification and readout cycles; means for identifying at least one from a plurality of different count modifiers in response to the digital count accumulated during said identification cycle; means for entering said at least one count modifier into said register means after said identification cycle and before said readout cycle; and means for reading out the digital count accumulated in said register means during said readout cycle as modified by said at least one count modifier.
Claim 13
Independent Claim
107 words
A system for generating a digital count as an output which is a function of an input variable comprising: register means for accumulating digital counts in response to the input during identification and readout cycles; means for identifying at least one from a plurality of different count modifiers in response to the digital count accumulated during said identification cycle; means for entering said at least one count modifier into said register means after said identification cycle and before said readout cycle; and means for reading out the digital count accumulated in said register means during said readout cycle as modified by said at least one count modifier.
Claim 14
Independent Claim
168 words
A system for generating a digital output which is a function of an analog input after two digitizing cycles comprising: a dual slope analog-to-digital converter generating gated clock pulses during first and second counting periods in each of said two digitizing cycles; register means for counting said pulses generated by said dual slope analog-to-digital converter during said first and second counting periods in each of said first and second digitizing cycles; means for identifying first and second count modifiers in response to the count in said register means at the end of said first digitizing cycle; means for clearing said register means after said first digitizing cycle; means for entering said first count modifier into said register means so as to affect the count accumulated during said first counting period of said second digitizing cycle; and means for entering said second count modifier into said register so as to affect the count accumulated during said second counting period of said second digitizing cycle to obtain the digitAl output.
Claim 15
Independent Claim
168 words
A system for generating a digital output which is a function of an analog input after two digitizing cycles comprising: a dual slope analog-to-digital converter generating gated clock pulses during first and second counting periods in each of said two digitizing cycles; register means for counting said pulses generated by said dual slope analog-to-digital converter during said first and second counting periods in each of said first and second digitizing cycles; means for identifying first and second count modifiers in response to the count in said register means at the end of said first digitizing cycle; means for clearing said register means after said first digitizing cycle; means for entering said first count modifier into said register means so as to affect the count accumulated during said first counting period of said second digitizing cycle; and means for entering said second count modifier into said register so as to affect the count accumulated during said second counting period of said second digitizing cycle to obtain the digitAl output.
Claim 16
Dependent Claim
80 words
The system of claim 10 wherein said means for identifying said first and second count modifiers comprises: a decoder for decoding a binary coded decimal representation of the count of said register means into a decimal representation; means for selecting said first and second count modifiers in response to the decoded decimal representation of the count; and an encoder for encoding the selected first and second count modifiers into a binary coded decimal representation before entry into said register means.
Claim 17
Independent Claim
196 words
A system for generating a digital output which is a function of an input variable after two digitizing cycles comprising: a digital transducer for generating variable frequency input pulses during said identification and readout cycles in response to said input variable; a main register means for counting said input pulses during said identification and readout cycles; a pulse generating means for generating fixed frequency reference pulses during said identification and readout cycles with the generation of said input pulses; an additional register means for counting said input pulses during said identification and readout cycles; means for identifying first and second count modifiers in response to the accumulated count in said main register means when the count in said additional register means reaches a predetermined number during said identification cycle; means for entering said first count modifier into said additional register means and entering said second count modifier into said main register means; and means for reading out the count accumulated within said main register means as modified by said second count modifier when the count accumulated in said additional register means as modified by said first count modifier reaches the predetermined number during said readout cycle.
Claim 18
Independent Claim
196 words
A system for generating a digital output which is a function of an input variable after two digitizing cycles comprising: a digital transducer for generating variable frequency input pulses during said identification and readout cycles in response to said input variable; a main register means for counting said input pulses during said identification and readout cycles; a pulse generating means for generating fixed frequency reference pulses during said identification and readout cycles with the generation of said input pulses; an additional register means for counting said input pulses during said identification and readout cycles; means for identifying first and second count modifiers in response to the accumulated count in said main register means when the count in said additional register means reaches a predetermined number during said identification cycle; means for entering said first count modifier into said additional register means and entering said second count modifier into said main register means; and means for reading out the count accumulated within said main register means as modified by said second count modifier when the count accumulated in said additional register means as modified by said first count modifier reaches the predetermined number during said readout cycle.
Claim 19
Dependent Claim
80 words
The system of claim 12 wherein said means for identifying said first and second count modifiers comprises: a decoder for decoding a binary coded decimal representation of the count of said register means into a decimal representation; means for selecting said first and second count modifiers in response to the decoded decimal representation of the count; and an encoder for encoding the selected first and second count modifiers into a binary coded decimal representation before entry into said register means.
Claim 20
Independent Claim
180 words
A method of generating a digital output as a nonlinear function of an analog input wherein the nonlinear function may be approximated by a plurality of linear segments between breakpoints on the nonlinear function and the linear segments have characteristic slopes and intercepts, the method comprising: accumulating a count at a substantially constant rate during a digital identification cycle for locating the analog input on said nonlinear function and identifying a particular one of the plurality of linear segments approximating said nonlinear function in the vicinity of said analog input; generating a first digital count modifier corresponding with the slope of said particular linear segment; generating a second digital count modifier corresponding to the intercept of said particular linear segment; accumulating a count at said substantially constant rate during a digital readout cycle; and modifying the length of said readout cycle with said first digital count modifier and modifying the accumulated count during said readout cycle with said second digital count modifier so as to obtain an accumulated count at the end of said readout cycle representing the digital output.
Claim 21
Independent Claim
180 words
A method of generating a digital output as a nonlinear function of an analog input wherein the nonlinear function may be approximated by a plurality of linear segments between breakpoints on the nonlinear function and the linear segments have characteristic slopes and intercepts, the method comprising: accumulating a count at a substantially constant rate during a digital identification cycle for locating the analog input on said nonlinear function and identifying a particular one of the plurality of linear segments approximating said nonlinear function in the vicinity of said analog input; generating a first digital count modifier corresponding with the slope of said particular linear segment; generating a second digital count modifier corresponding to the intercept of said particular linear segment; accumulating a count at said substantially constant rate during a digital readout cycle; and modifying the length of said readout cycle with said first digital count modifier and modifying the accumulated count during said readout cycle with said second digital count modifier so as to obtain an accumulated count at the end of said readout cycle representing the digital output.
Claim 22
Dependent Claim
194 words
A linearizing system for generating a digital output which is a nonlinear function of an analog input and may be approximated by a plurality of linear segments between breakpoints on the nonlinear function, each of the linear segments having characteristic slopes and intercepts, the system comprising: a means for producing a plurality of gated clock pulses from aN analog input during a first digitizing cycle and a second digitizing cycle; a register means for accumulating a count of gated clock pulses during the first digitizing cycle and the second digitizing cycle, the accumulated count of the first digitizing cycle identifying a breakpoint and the accumulated count at the end of the second digitizing cycle representing the digital output; a breakpoint circuit for identifying the breakpoint in response to the breakpoint identifying count in said register at the end of said first digitizing cycle; and a count modifier circuit for generating various count modifiers corresponding to each of said breakpoints, said count modifier circuit selecting count modifiers corresponding to the particular breakpoint identified by said breakpoint circuit for digitally modifying the count accumulated in said register means before the end of said second digitizing cycle.
Claim 23
Dependent Claim
194 words
A linearizing system for generating a digital output which is a nonlinear function of an analog input and may be approximated by a plurality of linear segments between breakpoints on the nonlinear function, each of the linear segments having characteristic slopes and intercepts, the system comprising: a means for producing a plurality of gated clock pulses from aN analog input during a first digitizing cycle and a second digitizing cycle; a register means for accumulating a count of gated clock pulses during the first digitizing cycle and the second digitizing cycle, the accumulated count of the first digitizing cycle identifying a breakpoint and the accumulated count at the end of the second digitizing cycle representing the digital output; a breakpoint circuit for identifying the breakpoint in response to the breakpoint identifying count in said register at the end of said first digitizing cycle; and a count modifier circuit for generating various count modifiers corresponding to each of said breakpoints, said count modifier circuit selecting count modifiers corresponding to the particular breakpoint identified by said breakpoint circuit for digitally modifying the count accumulated in said register means before the end of said second digitizing cycle.
Claim 24
Dependent Claim
21 words
The linearizing system of claim 15 wherein said means for producing a plurality of gated clock pulses comprises an analog-to-digital converter.
Claim 25
Dependent Claim
21 words
The linearizing system of claim 15 wherein said means for producing a plurality of gated clock pulses comprises a digital transducer.
Claim 26
Dependent Claim
98 words
The linearizing system of claim 17 further comprising an additional register for accumulating a count of reference clock pulses during the first digitizing cycle and the second digitizing cycle, the accumulated count in said additional register gating clock pulses produced by said digital transducer; and said count modifier circuit for selecting and generating count modifiers responsive to the breakpoint identified by said breakpoint circuit selects and generates one count modifier for digitally modifying the count accumulating in said register and another count modifier for digitally modifying the count accumulated in said additional register during said second digitizing cycle.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-22 | 1976-02-21 | 1976-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-22 | 1980-02-21 | 1980-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-22 | 1984-02-21 | 1984-08-22 | $7700.00 | Window Closed / Lapsed |