Patent US4364398A successfully refreshed from Google Patents.
US3683162A
Expired / Lapsed
US
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Digital filtering for detecting component frequencies from a set of predetermined frequencies
Assignee: Nokia Inc
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Filing: 1969-07-30
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Granted: 1972-08-08
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Expires: 1989-07-30
Abstract
Abstract A receiving device comprising a filtering section consisting of as many band-pass analysis filters as there are different component frequencies in the signals which can be received, and a processing section enabling an analysis of the energy in the individual filters.
Inventors
- 👤 Jean-Baptiste Jacob
- 👤 Pierre Lavanant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:12
CPC Classifications
H; H04; H04Q; H04Q1/00; H04Q1/18; H04Q1/30; H04Q1/44; H04Q1/444; H04Q1/45; H04Q1/457; H04Q1/4575
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
124 words
A numerical frequency analyzing apparatus for use in a telecommunication system comprising: means for receiving binary coded samples of voice frequency signals; and means for detecting component frequencies among each of a plurality of said frequency signals, the frequencies being detected from a predetermined number of frequencies including: a plurality of band-pass digital filters corresponding to said predetermined number of frequencies in the signals capable of being received, coupled to the output of said receiving means , means responsive to the outputs of said digital filters for determining the amount of energy in the outputs thereof, and means, responsive to said energy determining means, for selecting filters corresponding to component frequencies of each signal , the energies of which exceed a predetermined threshold level.
Claim 2
Dependent Claim
124 words
A numerical frequency analyzing apparatus for use in a telecommunication system comprising: means for receiving binary coded samples of voice frequency signals; and means for detecting component frequencies among each of a plurality of said frequency signals, the frequencies being detected from a predetermined number of frequencies including: a plurality of band-pass digital filters corresponding to said predetermined number of frequencies in the signals capable of being received, coupled to the output of said receiving means , means responsive to the outputs of said digital filters for determining the amount of energy in the outputs thereof, and means, responsive to said energy determining means, for selecting filters corresponding to component frequencies of each signal , the energies of which exceed a predetermined threshold level.
Claim 3
Dependent Claim
128 words
An apparatus according to claim 1, wherein said plurality of band-pass filters are formed from a combination of a computing circuit and a plurality of accessory store elements connected thereto, wherein said computing circuit receives an input signal sample X at a prescribed sampling frequency, and provides a first intermediate resultant quantity Y X - B2Y2 - B1Y1, where B1 and B2 represent first and second characteristic constant coefficients of a filter and Y1 and Y2 represent said quantity Y which has been delayed through first and second sampling delay periods, and an output quantity S Y - Y2 wherein the quantities B1,B2,Y1,Y2 are registered in said accessory store elements and wherein said energy determining means includes means for summing the sample outputs of said computing circuit .
Claim 4
Dependent Claim
218 words
An apparatus according to claim 2, wherein said computing circuit comprises: a first computing block means, responsive to the contents of said accessory store elements for combining said contents in the form of logarithmic quantities; a first converter means, responsive to the outputs of said first computing block means, for converting said logarithmic quantities into first linear quantities; a first register, responsive to the output of said first converter means for storing said first linear quantities; a second computing block means, responsive to the output of said first register, for combining said first linear quantities; a second register, responsive to the output of said second computing block means, for storing the output of said second computing block means in linear form; a third register, responsive to the output of said second computing block means and linear quantities representative of said input sample, for storing the inputs thereto, the outputs of said third register being connected to one input of said second computing block means; and a second converting means responsive to the outputs of said third register, for converting the contents thereof into logarithmic form and feeding said logarithmic quantities to one of said accessory store elements; and further including means for supplying timing signals to each element within said computing circuit for controlling the sequential operation thereof.
Claim 5
Dependent Claim
135 words
An apparatus according to claim 3, wherein said energy determining means comprises: said summing means including a detector-adder circuit, responsive to the output of said second register, for rectifying the amplitudes of the sample outputs thereof and summing said rectified amplitudes of a prescribed number of successive signal samples; a calculation store element, responsive to the summed sample outputs of said detector-adder circuit, for storing successive sum quantities of samples corresponding to the respective digital Filters; means, responsive to the stored sums in said calculation store element, for shifting and weighting said quantities and providing said shifted and weighted quantities at a plurality of respective outputs; and wherein said selecting means includes a maximum value testing circuit for determining, from among the outputs of said shifting means, the quantity having the maximum amount of energy.
Claim 6
Dependent Claim
101 words
An apparatus according to claim 4, wherein said plurality of accessory storage elements comprises first, second and third accessory store elements, said first accessory store element storing the logarithmic of said quantities Y and Y1, the output of said first accessory store being connected to said computing circuit and to the input of said second accessory store circuit for storing the logarithm of the quantity Y2, and wherein said third accessory store stores the logarithms of said characteristic filter constant coefficients B1 and B2 , the outputs of said second and third accessory store elements being connected to said computing circuit.
Claim 7
Dependent Claim
37 words
An apparatus in accordance with claim 4, wherein said detector adder circuit includes a first input connected to the output of said second register and a second input connected to the output of said calculation store element.
Claim 8
Dependent Claim
47 words
An apparatus in accordance with claim 6, wherein said selecting means includes means, responsive to the contents of said shifting means, for testing the ratio of the respective outputs thereof and for indicating the presence of a selected frequency only when said ratio exceeds a predetermined value.
Claim 9
Independent Claim
607 words
A method of analyzing samples of voice frequency signals comprising the steps of : a. simultaneously adding, in a first computing block means, the logarithms of a first quantity B2 of a band-pass digital filter provided in a plurality of band-pass digital filters corresponding to the respective different component frequencies in which useful information is contained and to which information signals are applied, a quantity Y2 corresponding to a quantity Y X - B2Y2 - B1 Y1 , which has been delayed through first and second sampling delay periods, where B1 and B2 represent first and second characteristic constant coefficients of a filter, and Y1 and Y2 represent said quantity Y which has been delayed through first and second sampling delay periods, respectively, the logarithms of said quantities Y1, Y2, B1 and B2 being stored in a plurality of accessory store elements , said first computing block means being responsive to the contents thereof in the form of logarithmic quantities, and storing an input sample X in a first register and, subsequently, converting in a first converter means, responsive to the output of said first computing block means, for converting the logarithmic quantity of said first computing block means into first linear quantities, the logarithmic sum of said output B2 and Y2 into a linear quantity B2 Y2 and storing said quantity B2 Y2 in a second register which is responsive to the output of said first converter means, during a first period of time; b. adding, in said first computing block means, the logarithm of the quantities B1 and Y1 and subtracting, in a second computing block means, which is responsive to the output of said second register, for combining said first linear quantities, the quantity B2 Y2 from the input signal sample X, simultaneously, and subsequently, converting the sum of the logarithms B1 and Y1 into a linear quantity B1 Y1 , in said first converter means, and storing said quantity B1 Y1 in said second rEgister, and storing the difference quantity X - B2 Y2 in said first register, during a second period of time; c. combining the linear quantities X - B2Y2 , and B1 Y1 in accordance with the equation Y X - B2 Y2 - B1 Y1 in said second computing block means, storing the logarithm of the quantity Y1 in one of said plurality of accessory store elements and applying the logarithm of the quantity Y2 to said first computing block means, simultaneously, and converting the logarithm of the quantity Y2 into a linear quantity in said first converter means and storing said linear quantity Y2 in said second register and, further storing in said first register said quantity Y, resulting from the combination of the linear quantities X, B2 Y2 and B1 Y1 in said second computing block means, during a third period of time; d. subtracting, in said second computing block means, the output quantity Y2 from the quantity Y, to product a difference quantity S and converting the quantity Y into logarithmic form in a second converter means which is responsive to the output of said first register, for converting the contents thereof into logarithmic form and feeding said logarithmic quantities to a second of said accessory store elements, and subsequently storing said quantity S in a third register, which is responsive to the output of said second computing block means, for storing the output of said second computing block means in linear form, and the logarithm of the quantity Y in said second of said accessory store elements, respectively during a fourth period of time; and repeating step (a) coincident with the execution of step (d).
Claim 10
Independent Claim
607 words
A method of analyzing samples of voice frequency signals comprising the steps of : a. simultaneously adding, in a first computing block means, the logarithms of a first quantity B2 of a band-pass digital filter provided in a plurality of band-pass digital filters corresponding to the respective different component frequencies in which useful information is contained and to which information signals are applied, a quantity Y2 corresponding to a quantity Y X - B2Y2 - B1 Y1 , which has been delayed through first and second sampling delay periods, where B1 and B2 represent first and second characteristic constant coefficients of a filter, and Y1 and Y2 represent said quantity Y which has been delayed through first and second sampling delay periods, respectively, the logarithms of said quantities Y1, Y2, B1 and B2 being stored in a plurality of accessory store elements , said first computing block means being responsive to the contents thereof in the form of logarithmic quantities, and storing an input sample X in a first register and, subsequently, converting in a first converter means, responsive to the output of said first computing block means, for converting the logarithmic quantity of said first computing block means into first linear quantities, the logarithmic sum of said output B2 and Y2 into a linear quantity B2 Y2 and storing said quantity B2 Y2 in a second register which is responsive to the output of said first converter means, during a first period of time; b. adding, in said first computing block means, the logarithm of the quantities B1 and Y1 and subtracting, in a second computing block means, which is responsive to the output of said second register, for combining said first linear quantities, the quantity B2 Y2 from the input signal sample X, simultaneously, and subsequently, converting the sum of the logarithms B1 and Y1 into a linear quantity B1 Y1 , in said first converter means, and storing said quantity B1 Y1 in said second rEgister, and storing the difference quantity X - B2 Y2 in said first register, during a second period of time; c. combining the linear quantities X - B2Y2 , and B1 Y1 in accordance with the equation Y X - B2 Y2 - B1 Y1 in said second computing block means, storing the logarithm of the quantity Y1 in one of said plurality of accessory store elements and applying the logarithm of the quantity Y2 to said first computing block means, simultaneously, and converting the logarithm of the quantity Y2 into a linear quantity in said first converter means and storing said linear quantity Y2 in said second register and, further storing in said first register said quantity Y, resulting from the combination of the linear quantities X, B2 Y2 and B1 Y1 in said second computing block means, during a third period of time; d. subtracting, in said second computing block means, the output quantity Y2 from the quantity Y, to product a difference quantity S and converting the quantity Y into logarithmic form in a second converter means which is responsive to the output of said first register, for converting the contents thereof into logarithmic form and feeding said logarithmic quantities to a second of said accessory store elements, and subsequently storing said quantity S in a third register, which is responsive to the output of said second computing block means, for storing the output of said second computing block means in linear form, and the logarithm of the quantity Y in said second of said accessory store elements, respectively during a fourth period of time; and repeating step (a) coincident with the execution of step (d).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-08-08 | 1976-02-07 | 1976-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-08-08 | 1980-02-07 | 1980-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-08-08 | 1984-02-07 | 1984-08-08 | $7700.00 | Window Closed / Lapsed |