US3679965A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply voltage output detector
Assignee: Pioneer Magnetics Inc
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Filing: 1971-02-25
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Granted: 1972-07-25
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Expires: 1991-02-25
Abstract
Abstract A circuit for use in conjunction with a power supply and which provides a first signal amplitude (e.g., logical ''''1'''') when the voltage output from the power supply is at or above its proper value, and which provides a second signal amplitude (e.g., logical ''''0'''') when the power supply voltage is below its proper value.
Inventors
- 👤 Bruce L Wilkinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:32
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/30
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
327 words
In combination with a power supply which produces a unidirectional voltage output, and which includes an output voltage sensing circuit, a power supply control circuit connected to the output of said sensing circuit for regulating said voltage output at a predetermined threshold level, a regulation detector circuit connected to the output of said voltage sensing circuit for producing a first logical output when said unidirectional voltage output from said power supply is below a predetermined level, and producing a second logical output when said power supply unidirectional voltage is above said threshold level, said regulation detector circuit comprising: an input circuit connected to the output of said voltage sensing circuit for sensing the level of the unidirectional voltage output therefrom; a first transistor having a base electrode connected to said input circuit, and having an emitter electrode connected to a point of reference potential, said first transistor assuming a first state when said unidirectional voltage output is above a predetermined level and assuming a second state when said unidirectional voltage output is below said preDetermined level; a second transistor having a base electrode connected to the collector electrode of said first transistor; an output circuit including a third transistor having a base electrode connected to the emitter electrode of said second transistor to assume a saturated state of conductivity when said first transistor is in one of its aforesaid states and to assume a non-conductive state when said first transistor is in the other of its aforesaid states; and a circuit including a resistor connected to a source of unidirectional potential and a capacitor connected to said resistor and to said point of reference potential, the common junction of said resistor and capacitor being connected to said collector electrode of said first transistor and to said base electrode of said second transistor for providing a delay in the transition of said third transistor between its aforesaid states as said unidirectional voltage output drops below the predetermined level.
Claim 2
Dependent Claim
327 words
In combination with a power supply which produces a unidirectional voltage output, and which includes an output voltage sensing circuit, a power supply control circuit connected to the output of said sensing circuit for regulating said voltage output at a predetermined threshold level, a regulation detector circuit connected to the output of said voltage sensing circuit for producing a first logical output when said unidirectional voltage output from said power supply is below a predetermined level, and producing a second logical output when said power supply unidirectional voltage is above said threshold level, said regulation detector circuit comprising: an input circuit connected to the output of said voltage sensing circuit for sensing the level of the unidirectional voltage output therefrom; a first transistor having a base electrode connected to said input circuit, and having an emitter electrode connected to a point of reference potential, said first transistor assuming a first state when said unidirectional voltage output is above a predetermined level and assuming a second state when said unidirectional voltage output is below said preDetermined level; a second transistor having a base electrode connected to the collector electrode of said first transistor; an output circuit including a third transistor having a base electrode connected to the emitter electrode of said second transistor to assume a saturated state of conductivity when said first transistor is in one of its aforesaid states and to assume a non-conductive state when said first transistor is in the other of its aforesaid states; and a circuit including a resistor connected to a source of unidirectional potential and a capacitor connected to said resistor and to said point of reference potential, the common junction of said resistor and capacitor being connected to said collector electrode of said first transistor and to said base electrode of said second transistor for providing a delay in the transition of said third transistor between its aforesaid states as said unidirectional voltage output drops below the predetermined level.
Claim 3
Dependent Claim
39 words
The combination defined in claim 1, in which said input circuit includes a resistance network to cause said first transistor to assume its first state at a level of said unidirectional voltage output slightly above the aforesaid predetermined level.
Claim 4
Dependent Claim
41 words
The combination defined in claim 1, and which includes a positive feedback network connected between said output circuit and said input circuit to increase the switching rate of said second transistor as said unidirectional voltage output rises above said predetermined level.
Claim 5
Dependent Claim
25 words
The combination defined in claim 1, in which said input circuit includes a filter network to render the detector circuit unresponsive to narrow noise pulses.
References Cited (Backward Citations)
US3098999A
Cited
US3225257A
Cited
US3354448A
Cited
US3534353A
Cited
US3586975A
Cited
US3599042A
Cited
US3584259A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-07-25 | 1976-01-24 | 1976-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-07-25 | 1980-01-24 | 1980-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-07-25 | 1984-01-24 | 1984-07-25 | $7700.00 | Window Closed / Lapsed |