Pulse analyzer

Claim 3

Time measuring apparatus comprising: first means to supply a periodic IN signal to be tested, said signal having high level portions and a low level portion between each two successive high level portions, one high level portion and one low level portion forming one complete cycle, said periodic signal having a frequency of a first predetermined number of said signal cycles per unit time; a pulse generator to supply pulses periodically with the time between two successive pulses forming one complete cycle, said pulses having a constant frequency of a second predetermined number of said cycles per the same said unit of time, said pulse frequency being large in comparison to said signal frequency and independent of the amplitude of said signal; second means for producing an output of a magnitude corresponding to the difference between the number of pulrses generated during a high level portion of said IN signal and the number of pulses generated during a low level portion of the self same said IN signal.

Claim 4

Time measuring apparatus comprising: first means to supply a periodic IN signal to be tested, said signal having high level portions and a low level portion between each two successive high level portions, one high level portion and one low level portion forming one complete cycle, said periodic signal having a frequency of a first predetermined number of said signal cycles per unit time; a pulse generator to supply pulses periodically with the time between two successive pulses forming one complete cycle, said pulses having a constant frequency of a second predetermined number of said cycles per the same said unit of time, said pulse frequency being large in comparison to said signal frequency and independent of the amplitude of said signal; second means for producing an output of a magnitude corresponding to the difference between the number of pulrses generated during a high level portion of said IN signal and the number of pulses generated during a low level portion of the self same said IN signal.

Claim 5

The invention as defined in claim 2, wherein the level of said periodic signal is approximately constant during any one portion, said second means including a first binary counter connected from said first means to produce a bi-level COUNT signal at one output which is high over alternate cycles of said IN signal and which is low the remainder of the time, said counter, at another output, also producing a STOP signal complement to said COUNT signal, and an inverter having an output, said inverter producing an IN signal complement to said IN signal, a reversible binary counter to produce an output in accordance with the number of pulses of one polarity introduced thereto minus the number of pulses introduced thereto of a polarity opposite said one polarity, a first AND gate having two inputs connected from said pulse generator and said COUNT output, respectively, said first AND gate having an output, third means responsive to said IN and IN signals to supply positive and negative pulses to said reversible counter at said pulse frequency; pulses of one polarity being supplied only while said IN signal is high, and pulses of the opposite polarity being supplied only when said IN is high, a storage register, a logic circuit, a second AND gate connected from said inverter IN output and from said STOP output to said logic circuit, said logic circuit having a plurality of third AND gates connected from each bit in said reversible counter to a corresponding bit in said storage register, all of said third gates transferring the contents of said reversible counter to said storage register upon receipt of a high level signal from said second AND gate, a fourth AND gate connected from said first means IN output and from said STOP output to said counter, a high output from said fourth AND gate causing said reversible counter to reset to zero, and means to indicate the state of said storage register.

Claim 6

The invention as defined in claim 2, wherein said second means includes a reversible counter, means to cause said counter to count the output pulses of said generator in one direction during a high level portion, and to count in the opposite direction during a low level portion.

Claim 7

The invention as defined in claim 2, including third means to store the output of said second means, and gating means actuable to transfer the output of said second means into said third means.

Claim 8

The invention as defined in claim 5, including means to actuate said gating means during a period not exceeding the period of said first means signal. >