Outgoing register sender system

Claim 2

In a PBX telephone system including at least one trunk circuit extending to a central exchange, a register sender system for controlling the transfer of digits of subscriber data to said central exchange via said trunk circuit comprising register sender means for storing and outpulsing said digits of subscriber data, digit analyzer means for analyzing the digits stored in said register sender means to determine whether said subscriber data relates to calls which are permitted for the subscriber attempting to establish the call, and control means responsive to the receipt and storage of subscriber data in said register sender means for connecting said digit analyzer means to said register sender means on a time shared basis.

Claim 3

A system as defined in claim 1, wherein said register sender means includes a main memory capable of storing selected data at a plurality of individually addressed storage areas, a steering-in counter for sequentially addressing the storage areas of said main memory to store data therein, and a steering-out counter for sequentially addressing the storage areas of said main memory to read-out data therein.

Claim 4

A system as defined in claim 2, wherein said register sender means further includes a temporary storage for a single digit and transfer means for automatically transferring the digit in said temporary storage to said main memory within a given time after receipt thereof in said temporary storage.

Claim 5

A system as defined in claim 3, wherein said transfer means includes means for automatically advancing said steering-in counter subsequent to transfer of a digit to said main memory.

Claim 6

A system as defined in claim 2, wherein said register sender means further includes first gating means responsive to control from said control means for connecting the storage areas of said main memory to said digit analyzer means in sequence.

Claim 7

A system as defined in claim 2, wherein said register sender means further includes impulse relay means for transmitting impulses through said trunk circuit to said central exchange and actuating means for applying clock pulses to actuate said impulse relay means for the number of times corresponding to a digit stored in said main memory.

Claim 8

A system as defined in claim 6, wherein said register sender means further includes an outpulsing counter, and means for pre-setting said outpulsing counter to the complement of a digit stored in said main memory, said actuating means also applying said clock pulses to said outpulsing counter to advance said counter, said outpulsing counter producing an output upon reaching a maximum count, which output is applied to said actuating means to inhibit further application of clock pulses to said impulse relay means.

Claim 9

A system as defined in claim 7, wherein said register sender means further includes means responsive to said outpulsing counter reaching said final count for resetting said outpulsing counter and advancing said steering-out counter after a given delay period.

Claim 10

A system as defined in claim 6, wherein said register sender means further includes data detection means for inhibiting said actuating means so long as no data is stored in said main memory.

Claim 11

A system as defined in claim 6, wherein said register sender means further includes demand evaluation means responsive to said digit analyzer means for inhibiting said actuating means until the digits stored in said main memory have been analyzed and approved by said digit analyzer means.

Claim 12

A system as defined in claim 2, wherein said digit analyzer means includes storage means for storing a plurality of digits received from said register sender means and analyzing means for determining from the digits in said storage means the total number of digits which the register sender means can be expected to receive.

Claim 13

A system as defined in claim 11, wherein said register sender means includes second gating means for connecting the output of said steering-in counter representing the number of digits received by the register sender system to said digit analyzer means, said digit analyzer means including comparison means for providing a signal to said digit analyzer means indicating that all digits have been received in response to the output of said steering-in counter corresponding to the output of said analyzing means.

Claim 14

A system as defined in claim 1, wherein said digit analyzing means includes office code decoding means for detecting whether the received digits in said register sender means relate to an acceptable office code.

Claim 15

A system as defined in claim 13, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and said office code decoding means includes means for inhibiting said call abandonment means upon detecting digits relating to an acceptable office code.

Claim 16

A system as defined in claim 1, wherein said digit analyzing means includes area code decoding means for detecting whether the received digits in said register sender means relate to an acceptable area code.

Claim 17

A system as defined in claim 15, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and said area code decoding means includes means for inhibiting said call abandonment means upon detecting digits relating to an acceptable office code.

Claim 18

A system as defined in claim 1, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and service code detecting means for inhibiting said call abandonment means upon detection of a dialed service code.

Claim 19

A system as defined in claim 1, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and operator code detecting means for inhibiting said call abandonment means upon detection of a dialed call to the operator.

Claim 20

A system as defined in claim 1, wherein said register sender means includes a plurality of register senders each including a main memory capable of storing selected data at a plurality of individually addressed storage areas, said control means including scanning means for scanning said register senders with a scanning signal in sequence, each register sender including demand evaluation means responsive to receipt of a scanning signal from said control means for applying a stop signal thereto to stop said scanning means.

Claim 21

A system as defined in claim 19, wherein said register sender means further includes first gating means responsive to control from said control means for connecting the storage areas of said main memory to said digit analyzer means in sequence.

Claim 22

A system as defined in claim 20, wherein said control means further includes counter means actuated by said stop signal for applying in sequence numerical value signals of increasing value in control of said firsT gating means.

Claim 23

A system as defined in claim 21, wherein said control means further includes third gating means responsive to said counter means reaching a maximum count for automatically actuating said scanning means.

Claim 24

A system as defined in claim 11, wherein said storage means in said digit analyzer means includes only three single digit storages, and said digit analyzer further includes steering means responsive to said analyzing means for steering digits received in sequence into said three single digit storages so that digits representing area codes and office codes are inserted in order beginning always with the first single digit storage.

Claim 25

A system as defined in claim 23, wherein said digits received in said digit analyzer means from said register sender means are applied to each of said single digit storages through a respective fourth gating means, said steering means including means for generating steering signals capable of enabling selected one of said fourth gating means in an order of said single digit storages required by the digits received.

Claim 26

A register sender for an automatic telephone system comprising a main memory capable of storing selected data at a plurality of individually addressed storage areas, a steering-in counter for sequentially addressing the storage areas of said main memory to store data therein, a steering-out counter for sequentially addressing the storage areas of said main memory to read-out data therein, a temporary storage for a single digit, and transfer means for automatically transferring a digit in said temporary storage to said main memory within a given time after receipt thereof in said temporary storage.

Claim 27

A register sender for an automatic telephone system comprising a main memory capable of storing selected data at a plurality of individually addressed storage areas, a steering-in counter for sequentially addressing the storage areas of said main memory to store data therein, a steering-out counter for sequentially addressing the storage areas of said main memory to read-out data therein, a temporary storage for a single digit, and transfer means for automatically transferring a digit in said temporary storage to said main memory within a given time after receipt thereof in said temporary storage.

Claim 28

A system as defined in claim 25, wherein said transfer means includes means for automatically advancing said steering-in counter subsequent to transfer of a digit to said main memory.

Claim 29

A system as defined in claim 25, wherein said register sender means further includes impulse relay means for transmitting impulses through said trunk circuit to said central exchange and actuating means for applying clock pulses to actuate said impulse relay means for the number of times corresponding to a digit stored in said main memory.

Claim 30

A system as defined in claim 27, wherein said register sender means further includes an outpulsing counter, and means for pre-setting said outpulsing counter to the complement of a digit stored in said main memory, said actuating means also applying said clock pulses to said outpulsing counter to advance said counter, said outpulsing counter producing an output upon reaching a final count, which output is applied to said actuating means to inhibit further application of clock pulses to said impulse relay means.

Claim 31

A system as defined in claim 28, wherein said register sender means further includes means responsive to said outpulsing counter reaching said final count for resetting said outpulsing counter and advancing said steering-out counter after a given delay period.

Claim 32

A system as defined in claim 29, wherein said register sender means further includes data detection means for inhibiting said actuating means so long as no data is stored in said main memory.

Claim 33

A system as defined in claim 27, wherein said register sender means further includes demand evaluation means for inhibiting said actuating means until the digits stored in said main memory have been analyzed and approved.

Claim 34

In a PBX telephone system including at least one trunk circuit extending to a central exchange, a register sender system for controlling the transfer of digits of subscriber data to said central exchange via said trunk circuit comprising register sender means for storing an outpulsing said digits of subscriber data, and digit analyzer means for analyzing the digits stored in said register sender means to determine whether said subscriber data relates to calls which are permitted for the subscriber attempting to establish the call, said register sender means including a main memory capable of storing selected data at a plurality of individually addressed storage areas, a steering-in counter for sequentially addressing the storage areas of said main memory to store data therein, and a steering-out counter for sequentially addressing the storage areas of said main memory to read-out data therein.

Claim 35

In a PBX telephone system including at least one trunk circuit extending to a central exchange, a register sender system for controlling the transfer of digits of subscriber data to said central exchange via said trunk circuit comprising register sender means for storing an outpulsing said digits of subscriber data, and digit analyzer means for analyzing the digits stored in said register sender means to determine whether said subscriber data relates to calls which are permitted for the subscriber attempting to establish the call, said register sender means including a main memory capable of storing selected data at a plurality of individually addressed storage areas, a steering-in counter for sequentially addressing the storage areas of said main memory to store data therein, and a steering-out counter for sequentially addressing the storage areas of said main memory to read-out data therein.

Claim 36

A system as defined in claim 32, wherein said digit analyzer means includes storage means for storing a plurality of digits received from said register sender means and analyzing means for determining from the digits in said storage means the total number of digits which the register sender means can be expected to receive.

Claim 37

A system as defined in claim 33, wherein said register sender means includes second gating means for connecting the output of said steering-in counter representing the number of digits received by the register sender system to said digit analyzer means, said digit analyzer means including comparison means for providing a signal to said digit analyzer means indicating that all digits have been received in response to the output of said steering-in counter corresponding to the output of said analyzing means.

Claim 38

A system as defined in claim 34, wherein said digit analyzing means includes office code decoding means for detecting whether the received digits in said register sender means relate to an acceptable office code.

Claim 39

A system as defined in claim 35, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and said office code decoding means includes means for inhibiting said call abandonment means upon detecting digits relating to an acceptable office code.

Claim 40

A system as defined in claim 34, wherein said digit analyzing means includes area code decoding means for detecting whether the received digits in said register sender means relate to an acceptable area code.

Claim 41

A system as defined in claim 37, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and said area code decoding means includes means for inhibiting said call abandonment means upon detecting digits relating to an acceptable office code.

Claim 42

A system as defined in claim 34, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and service code detecting means for inhibiting said call abandonment means upon detection of a dialed service code.

Claim 43

A system as defined in claim 34, wherein said digit analyzing means includes call abandonment means for abandoning a call after a certain time period during the dialing of a call and operator code detecting means for inhibiting said call abandonment means upon detection of a dialed call to the operator.

Claim 44

A system as defined in claim 33, wherein said storage means in said digit analyzer means includes only three single digit storages, and said digit analyzer further includes steering means responsive to said analyzing means for steering digits received in sequence into said three single digit storages so that digits representing area codes and office codes are inserted in order beginning always with the first single digit storage.

Claim 45

A system as defined in claim 41, wherein said digits received in said digit analyzer means from said register sender means are applied to each of said single digit storages through a respective fourth gating means, said steering means including means for generating steering signals capable of enabling selected one of said fourth gating means in an order of said single digit storages required by the digits received.

Claim 46

A system as defined in claim 34, wherein said register sender means further includes a temporary storage for a single digit and transfer means for automatically transferring the digit in said temporary storage to said maIn memory within a given time after receipt thereof in said temporary storage.

Claim 47

A system as defined in claim 43, wherein said transfer means includes means for automatically advancing said steering-in counter subsequent to transfer of a digit to said main memory.

Claim 48

A system as defined in claim 44, wherein said register sender means further includes first gating means responsive to control from said control means for connecting the storage areas of said main memory to said digit analyzer means in sequence.

Claim 49

A system as defined in claim 45, wherein said register sender means further includes impulse relay means for transmitting impulses through said trunk circuit to said central exchange and actuating means for applying clock pulses to actuate said impulse relay means for the number of times corresponding to a digit stored in said main memory.

Claim 50

A system as defined in claim 46, wherein said register sender means further includes an outpulsing counter, and means for pre-setting said outpulsing counter to the complement of a digit stored in said main memory, said actuating means also applying said clock pulses to said outpulsing counter to advance said counter, said outpulsing counter producing an output upon reaching a final count, which output is applied to said actuating means to inhibit further application of clock pulses to said impulse relay means.

Claim 51

A system as defined in claim 47, wherein said register sender means further includes means responsive to said outpulsing counter reaching said final count for resetting said outpulsing counter and advancing said steering-out counter after a given delay period.

Claim 52

A system as defined in claim 46, wherein said register sender means further includes data detection means for inhibiting said actuating means so long as no data is stored in said main memory.

Claim 53

A system as defined in claim 46, wherein said register sender means further includes demand evaluation means responsive to said digit analyzer means for inhibiting said actuating means until the digits stored in said main memory have been analyzed and approved by said digit analyzer means.

Claim 54

In a PBX telephone system including at least one trunk circuit extending to a central exchange, a register sender system for controlling the transfer of digits of subscriber data to said central exchange via said trunk circuit comprising register sender means for storing and outpulsing said digits of subscriber data, including at least one register sender having a main memory capable of storing selected data at a plurality of individually addressed storage areas, digit analyzer means for analyzing the digits stored in said register sender means to determine whether said subscriber data relates to calls which are permitted for the subscriber attempting to establish the call, and control means responsive to the receipt and storage of subscriber data in said register sender means for connecting said digit analyzer means to said register sender means, said register sender further including a temporary stroage for a single digit and transfer means for automatically transferring the digit in said temporary storage to said main memory within a given time after receipt thereof in said temporary storage.

Claim 55

In a PBX telephone system including at least one trunk circuit extending to a central exchange, a register sender system for controlling the transfer of digits of subscriber data to said central exchange via said trunk circuit comprising register sender means for storing and outpulsing said digits of subscriber data, including at least one register sender having a main memory capable of storing selected data at a plurality of individually addressed storage areas, digit analyzer means for analyzing the digits stored in said register sender means to determine whether said subscriber data relates to calls which are permitted for the subscriber attempting to establish the call, and control means responsive to the receipt and storage of subscriber data in said register sender means for connecting said digit analyzer means to said register sender means, said register sender further including a temporary stroage for a single digit and transfer means for automatically transferring the digit in said temporary storage to said main memory within a given time after receipt thereof in said temporary storage.

Claim 56

A system as defined in claim 51, wherein said register sender means includes a plurality of register senders each including a main memory capable of storing selected data at a plurality of individually addressed storage areas, said control means including scanning means for scanning said register senders with a scanning signal in sequence, each register sender including demand evaluation means responsive to receipt of a scanning signal from said control means for applying a stop signal thereto to stop said scanning means.

Claim 57

A system as defined in claim 52, wherein said register senders each include means for inhibiting said demand evaluation means from generating said stop signal so long as said transfer means is operating to transfer data into said main memory.

Claim 58

A system as defined in claim 52, wherein said register senders each further include means for connecting said main memory of a given register to said digit analyzer means.

Claim 59

A system as defined in claim 54, wherein said control means further includes counter means actuated by said stop signal for applying in sequence numerical value signals of increasing value in control of said first gating means.

Claim 60

A system as defined in claim 55, wherein said control means further includes third gating means responsive to said counter means reaching a maximum count for automatically actuating said scanning means.

Claim 61

A system as defined in claim 51, wherein said register senders each further include means for continuously clearing the main memory thereof so long as the particular register sender is not connected to a trunk circuit.