Single package basic processor unit with synchronous and asynchronous timing control

Claim 2

A basic processor unit for use in a data processing system comprising in combination: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element adapted to operate in a synchronous or an asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; and means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit.

Claim 3

The invention in accordance with claim 1 wherein said timing control includes an oscillator having a feedback paTh; a multi-phase time signal generator comprising a plurality of bistable elements; and a counter adapted to advance with each oscillation of said oscillator; said oscillator including a first delay device having an output connected to said counter and an input connected to a multiple input logic gate having at least one input for each phase, each input of said gate being connected to a second logic gate, said second logic gates each having on input connected to the feedback path of said oscillator, a second input connected to the means for controlling said asynchronous mode, and a third input connected to the corresponding phase of said multi-phase time signal generator; and a second delay device having an input connected to the output of said first delay device and an output connected to said multi-phase time signal generator.

Claim 4

The invention in accordance with claim 1 wherein said arithmetic unit has an initial carry input and a final carry output, at least one bistable element operationally connected to said final carry output, and gating for the output of said bistable element adapted to be enabled or disabled.

Claim 5

The invention in accordance with claim 3 further including a second bistable element, said second element operatively connected to the output of the most significant bit of said arithmetic unit and gating for the output of said second bistable element adapted to be enabled and disabled.

Claim 6

The invention in accordance with claim 4 further including a logic element having an input connected to each bit of said output bus and an output operatively connected to a third bistable element whereby to detect the presence of either zero or non-zero resultant from said arithmetic unit and gating for the output of said third bistable element adapted to be enabled or disabled.

Claim 7

The invention in accordance with claim 1 wherein said input bus and said output bus each have at least one bit corresponding to each bit of said registers; said input bus bits are connected to the corresponding output bus bits through a buffer; and means for external connections for all bits of one of said buses.

Claim 8

The invention in accordance with claim 1 further comprising a first operand register having an input connected to said input bus and output connected to said data processing unit and a second operand register having a first input connected to said input bus, a second input connected to said output bus and an output connected to said data processing unit.

Claim 9

The invention in accordance with claim 1 further comprising a second output bus having a bit corresponding to each bit of said registers; a second input bus having a bit corresponding to each bit of said registers; and a second buffer interconnecting each bit of said second output bus to the corresponding bit of said second input bus.

Claim 10

The invention in accordance with claim 8 further comprising a third output bus connected to each bit of the output of said registers.

Claim 11

The invention in accordance with claim 1 wherein said data processing unit further includes a bit manipulation unit for logic operations and a shift unit.

Claim 12

The invention in accordance with claim 1 wherein said data processing unit includes a logic gating for shifting its output one bit to the left or one bit to the right and said output bus includes a bit position corresponding to the shift left and shift right outputs of said data processing unit.

Claim 13

A processor unit comprising in combination a first basic processor unit and a second basic processor unit, each said basic processor unit comprising: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element aDapted to operate in a synchronous or an asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit; and, means connecting the bits of the first basic processor unit output bus in parallel to the corresponding bits of the second basic processor unit output bus whereby the total number of data processing units and data storage units is double that each basic processor unit.

Claim 14

A processor unit comprising in combination a first basic processor unit and a second basic processor unit, each said basic processor unit comprising: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element aDapted to operate in a synchronous or an asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit; and, means connecting the bits of the first basic processor unit output bus in parallel to the corresponding bits of the second basic processor unit output bus whereby the total number of data processing units and data storage units is double that each basic processor unit.

Claim 15

A processor unit comprising in combination a first basic processor unit and a second basic processor unit, said processor unit having twice the number of bits of said basic processor units individually, each said basic processor unit comprising: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element adapted to operate in a synchronous or asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; and means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit; wherein each of said arithmetic units includes: an initial input carry and a final output carry, a first bistable element operatively connected to said final output carry, and gating for the output of said bistable element adapted to be enabled or disabled; a second bistable element, said second element operatively connected to the output of the most significant bit of said arithmetic unit, and said gating for the output of said second bistable element adapted to be enabled or disabled; and logic gating for shifting the output of said data processing unit one bit to the left or right; each of said output buses includes a bit corresponding to the shift left or shift right output, the overlapping bits of said output buses are connected together whereby the resultant combined output bus has only one shift left bit position and one shift right bit position; and said first and second bistable elements of the least significant basic processor unit are disabled, and the control source and timing control of both said basic processor units are connected in parallel.

Claim 16

A processor unit comprising in combination a first basic processor unit and a second basic processor unit, said processor unit having twice the number of bits of said basic processor units individually, each said basic processor unit comprising: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element adapted to operate in a synchronous or asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; and means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit; wherein each of said arithmetic units includes: an initial input carry and a final output carry, a first bistable element operatively connected to said final output carry, and gating for the output of said bistable element adapted to be enabled or disabled; a second bistable element, said second element operatively connected to the output of the most significant bit of said arithmetic unit, and said gating for the output of said second bistable element adapted to be enabled or disabled; and logic gating for shifting the output of said data processing unit one bit to the left or right; each of said output buses includes a bit corresponding to the shift left or shift right output, the overlapping bits of said output buses are connected together whereby the resultant combined output bus has only one shift left bit position and one shift right bit position; and said first and second bistable elements of the least significant basic processor unit are disabled, and the control source and timing control of both said basic processor units are connected in parallel.

Claim 17

A data processing system comprising: a main storage memory including storage elements, at least one data register, at least one address register, and control logic; a first processor connected to said storage memory to receive and transmit data instructions therefrom; a first control memory including storage elements, at least one data register, at least one address register, and control logic; means interconnecting said first processor and said first control memory; means interconnecting said first control memory and said first processor; a second processor connected to said storage memory to receive and transmit data instructions therefrom; a second control memory including storage elements, at least one data register, at least one address register, and control logic; means interconnecting said second processor and said second control memory; at least one input-output control connected to said second processor; and said first and second processors are free of direct interconnection therebetween.

Claim 18

A data processing system comprising: a main storage memory including storage elements, at least one data register, at least one address register, and control logic; a first processor connected to said storage memory to receive and transmit data instructions therefrom; a first control memory including storage elements, at least one data register, at least one address register, and control logic; means interconnecting said first processor and said first control memory; means interconnecting said first control memory and said first processor; a second processor connected to said storage memory to receive and transmit data instructions therefrom; a second control memory including storage elements, at least one data register, at least one address register, and control logic; means interconnecting said second processor and said second control memory; at least one input-output control connected to said second processor; and said first and second processors are free of direct interconnection therebetween.

Claim 19

The data processing system in accordance with claim 14 wherein each of said processors includes at least one basic processor unit, said basic processor unit comprising: a data storage unit including a plurality of registers and the input and output gating for said registers; an output bus and an input bus; a data processing unit including an arithmetic unit and the gating for said arithmetic unit, said data processing unit having an input connected to said data storage unit through said buses and an output connected to said output bus; a timing control including a timing element adapted to operate in synchronous or asynchronous mode; means for controlling the asynchronous operation of said timing element; decoding means having an input connected to a control source; means for externally connecting said buses; at least one register of said data storage unit connected to said input bus; at least one register of said data storage unit connected to said output bus; and means for connecting the output of said decoding means and the output of said timing control to said data storage unit and said data processing unit; wherein, said means for controlling the asynchronous operation of said timing element is connected to the main memory and the first control memory; said decoding means is connected to the output of the data register of said first control memory; and said means for externally connecting said buses is connected to the data register of said main memory.