Method of controlling jumps to different programs in a computer working in real time

Claim 3

The method as claimed in claim 1, wherein said comparing comprises subtracting the contents of said clock register from said number in a binary form and the passing of said value is indicated by the most significant bit of the comparison result being a particular binary value.

Claim 4

In a computer operating in real time wherein a plurality of programs associated with different priority levels are sequentially executed within primary intervals, the programs associated with the different priority levels being selected at times which are different multiples of a primary interval, apparatus for controlling jumps to said programs comprising: a pulse generator for emitting pulses defining said primary intervals, a clock register for accumulating said pulses for counting said primary intervals, a memory including a plurality of memory fields, each of said memory fields being associated with a different one of said programs, each of said memory field means including a first register for storing a clock register value which determines the primary interval during which the next selection of the associated program is to be performed after a previous selection and a second register for storing the starting address of the associated program, a decoder means having a plurality of inputs and outputs, an arithmetic unit comprising a first operand register connected to said clock register for storing the instantaneous value of said clock register, a second operand register, a result register, means responsive to a compare control signal for performing a comparison between the contents of operand registers and for storing the results thereof in said result register, and means responsive to an add control signal for adding the contents of said operand registers and storing the sum thereof in said result register, means for generating said compare control signal, a multi-stage shift register including a presetting input connected to said pulse generator for setting the shift register to a particular stage, a step input for stepping the shift to the next stage of the sequence, and an output associated with each stage, each stage of said shift register being associated with a different one of said programs, means connected to the outputs of the stages of said shift register for transferring the contents of the said first register associated with the output of the stage of said shift register which is activated to said second operand register, means connected to the ouTputs of the stages of said shift register and responsive to said add control signal for transferring the contents of said result register to the one of said first registers associated with the stage of said shift register which is activated, comparison-result indicating means connected to said result register and responsive to said compare signal for generating a first control signal when the contents of said second operand register is greater than the contents of said first operand register and a second control signal when they are not, means responsive to the presence of said first control signal for transferring the contents of the second register associated with the then activated stage of said shift register to an input of said decoder means, means responsive to the presence of said second control signal for transmitting a pulse to the stepping input of said shift register whereby said first register of the subsequent memory field is selected to transfer its contents to said second operand register, an addressed memory for storing each of the programs in a different sequence of memory registers, storage means associated with each of said sequences for storing a number related to the number of primary intervals which must elapse before the associated program is to be performed, said decoder means including means operative upon receipt of a starting address from one of said second registers to initiate the operation of the program associated therewith and said decoder means further including means for transferring the contents of the said storage means of the said program to said operand register and generating said add signal.

Claim 5

In a computer operating in real time wherein a plurality of programs associated with different priority levels are sequentially executed within primary intervals, the programs associated with the different priority levels being selected at times which are different multiples of a primary interval, apparatus for controlling jumps to said programs comprising: a pulse generator for emitting pulses defining said primary intervals, a clock register for accumulating said pulses for counting said primary intervals, a memory including a plurality of memory fields, each of said memory fields being associated with a different one of said programs, each of said memory field means including a first register for storing a clock register value which determines the primary interval during which the next selection of the associated program is to be performed after a previous selection and a second register for storing the starting address of the associated program, a decoder means having a plurality of inputs and outputs, an arithmetic unit comprising a first operand register connected to said clock register for storing the instantaneous value of said clock register, a second operand register, a result register, means responsive to a compare control signal for performing a comparison between the contents of operand registers and for storing the results thereof in said result register, and means responsive to an add control signal for adding the contents of said operand registers and storing the sum thereof in said result register, means for generating said compare control signal, a multi-stage shift register including a presetting input connected to said pulse generator for setting the shift register to a particular stage, a step input for stepping the shift to the next stage of the sequence, and an output associated with each stage, each stage of said shift register being associated with a different one of said programs, means connected to the outputs of the stages of said shift register for transferring the contents of the said first register associated with the output of the stage of said shift register which is activated to said second operand register, means connected to the ouTputs of the stages of said shift register and responsive to said add control signal for transferring the contents of said result register to the one of said first registers associated with the stage of said shift register which is activated, comparison-result indicating means connected to said result register and responsive to said compare signal for generating a first control signal when the contents of said second operand register is greater than the contents of said first operand register and a second control signal when they are not, means responsive to the presence of said first control signal for transferring the contents of the second register associated with the then activated stage of said shift register to an input of said decoder means, means responsive to the presence of said second control signal for transmitting a pulse to the stepping input of said shift register whereby said first register of the subsequent memory field is selected to transfer its contents to said second operand register, an addressed memory for storing each of the programs in a different sequence of memory registers, storage means associated with each of said sequences for storing a number related to the number of primary intervals which must elapse before the associated program is to be performed, said decoder means including means operative upon receipt of a starting address from one of said second registers to initiate the operation of the program associated therewith and said decoder means further including means for transferring the contents of the said storage means of the said program to said operand register and generating said add signal.