Patent WO1993017635A1 successfully refreshed from Google Patents.
US3662163A
Expired / Lapsed
US
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Digital signal linearizer
Assignee: General Electric Co
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Filing: 1970-08-04
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Granted: 1972-05-09
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Expires: 1990-08-04
Abstract
Abstract A digital signal linearizer for obtaining a linear digital output from a non-linear input. The input voltage is a non-linear representation of a quantity, such as temperature as measured by a thermocouple sensor. A voltage controlled oscillator converts the input voltage to a pulse train having a pulse rate which is a linear representation of the input voltage, but like the input voltage, is a non-linear representation of the measured quantity. The pulses are connected through a NAND gate to programmable divided by N frequency divider for fixed repeated intervals. Hence, the number of pulses passed depends directly on the repetition rate of the oscillator output pulses. Since the voltage, and hence pulse rate v. Quantity measured characteristics of the sensor are known, the divider is programmed to provide a division factor n which varies over different segment of the range of interest so that the output pulse count from the divider is linearly related to the quantity being measured.
Inventors
- 👤 David E Miller
- 👤 Robert C Heil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 21:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G06F17/00; G06F17/10; G06F17/17; H; H03; H03M; H03M1/00; H03M1/12; H03M1/60; H03M1/62
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
199 words
A digital signal linearizer comprised of a. Input means to a sensor and for providing a digital representation in the form of output pulses the repetition rate of which varies with the quantity being measured by the sensor and with the said variations being non linear; b. A programmable frequency divider; c. Means for coupling the output of said input means to said programmable frequency divider; d. Counting means coupled to the output frequency divider and having an output for coupling to the output frequency utilization means whereby the registered count in said counting means represents the quantity being measured; and, e. Means for varying the division factor of said divider for different individual segments of the range of value of the quantity being measured, including means for actuating the change in division factor after a series of individual predetermined counts with each of said individual counts representing the individual selected segments of said range, the division factor for each segment being such that the output of said counter per unit of the quantity being measured is constant over the entire range of value whereby the output applied to any utilization means varies linearly with the quantity being measured.
Claim 2
Dependent Claim
199 words
A digital signal linearizer comprised of a. Input means to a sensor and for providing a digital representation in the form of output pulses the repetition rate of which varies with the quantity being measured by the sensor and with the said variations being non linear; b. A programmable frequency divider; c. Means for coupling the output of said input means to said programmable frequency divider; d. Counting means coupled to the output frequency divider and having an output for coupling to the output frequency utilization means whereby the registered count in said counting means represents the quantity being measured; and, e. Means for varying the division factor of said divider for different individual segments of the range of value of the quantity being measured, including means for actuating the change in division factor after a series of individual predetermined counts with each of said individual counts representing the individual selected segments of said range, the division factor for each segment being such that the output of said counter per unit of the quantity being measured is constant over the entire range of value whereby the output applied to any utilization means varies linearly with the quantity being measured.
Claim 3
Dependent Claim
97 words
The digital linearizer according to claim 1 wherein the means for varying the division factor includes; a programming control logic coupled to said counting means and providing an output coupled to said frequency divider for setting the divisor or said programmable frequency divider in response to predetermined counts in said counting means, said programming control logic being presettable to produce output control signals in response to each of the predetermined counts, said control signals varying with different predetermined counts for establishing different divisors whereby said counter provides a linear output with respect to the quantity being measured.
Claim 4
Dependent Claim
18 words
A digital signal linearizer according to claim 2 in which said input means comprises a voltage controlled oscillator.
Claim 5
Dependent Claim
54 words
A digital signal linearizer according to claim 3 in which said coupling means comprises means for gating the output of said voltage controlled oscillator into said programmable frequency divider for a fixed period of time and further comprising means for periodically resetting said counting means after the end of each fixed period of time.
Claim 6
Dependent Claim
77 words
A digital signal linearizer according to claim 4 in which said coupling means comprises a NAND gate having a first input connected to the output of said voltage controlled oscillator, a second input for connection to a clock oscillator, and an output connected to said programmable frequency divider, and in which said means for resetting comprises a logic circuit having an input for connection to the clock oscillator and an output connected for resetting said counting means.
Claim 7
Dependent Claim
55 words
A digital signal linearizer according to claim 5 further comprising register means coupled to the output of said counting means, means for periodically resetting said register means after each period of time, and decoding means connected to the output of said register mEans, and readout display means coupled to the output of said decoding means.
Claim 8
Dependent Claim
64 words
The digital signal linearizers according to claim 1 in which said input means comprises a voltage controlled oscillator for producing a train of pulses having a repetition rate proportional to the quantity being measured and gating for coupling the pulses into said programmable divider for a fixed time period, and means for resetting the counting means at the end of each fixed time period.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-05-09 | 1975-11-08 | 1976-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-05-09 | 1979-11-08 | 1980-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-05-09 | 1983-11-08 | 1984-05-09 | $7700.00 | Window Closed / Lapsed |