Data insertion system

Claim 2

In a borehole system having borehole means for providing logic data signals and for transmitting such logic data signals over a single conductor to the surface: borehole means for storing said logic data signals; single conductor means for supplying a power signal from the surfAce to said borehole means; means for detecting said stored logic data signals and superimposing said detected logic data signals on said power signal; and surface means for separating said logic data signals from said power signal.

Claim 3

The system of claim 1 and further including means for generating second logic signals and means for superimposing said second logic signals on said power signal in phase spaced relationship.

Claim 4

The system of claim 2 wherein said second logic signals are superimposed on said power signal to separate portions of said logic data signals superimposed thereon.

Claim 5

The system of claim 3 and further including surface means for separating said logic data signal and second logic signal from said power signal and means for comparing said logic data signals and second logic signal with said power signal to differentiate between said logic signals.

Claim 6

A circuit system for inserting logic signals on a conductor including: means for providing a line signal on said conductor; means for providing a logic signal to said circuit system; switch means responsive to said logic signal for providing an output pulse in time relation with a fixed predetermined phase position on said line signal; and reactive means positioned between and in series with said switch means and said conductor for inserting a logic signal on said conductor in phase relation with said fixed predetermined phase position.

Claim 7

A circuit system for inserting logic signals on a conductor including: means for providing a line signal on said conductor; means for providing a logic signal to said circuit system; switch means responsive to said logic signal for providing an output pulse in time relation with a fixed predetermined phase position on said line signal; and reactive means positioned between and in series with said switch means and said conductor for inserting a logic signal on said conductor in phase relation with said fixed predetermined phase position.

Claim 8

In a circuit system for inserting logic signals on a conductor, including: means for providing a line signal on said conductor; means for providing data logic signals to said circuit system; means for providing synchronization logic signals to said circuit system, said data logic signals being time coordinated with a first position on the line signal, said synchronization logic signal being time coordinated with a second position on the line signal which is phase spaced from said first position; means responsive to said data logic signal for superimposing a pulse on said line signal at a first fixed predetermined phase position; and means responsive to said synchronization logic signal for superimposing a pulse on said line signal at a second fixed predetermined phase position.

Claim 9

In a circuit system for inserting logic signals on a conductor, including: means for providing a line signal on said conductor; means for providing data logic signals to said circuit system; means for providing synchronization logic signals to said circuit system, said data logic signals being time coordinated with a first position on the line signal, said synchronization logic signal being time coordinated with a second position on the line signal which is phase spaced from said first position; means responsive to said data logic signal for superimposing a pulse on said line signal at a first fixed predetermined phase position; and means responsive to said synchronization logic signal for superimposing a pulse on said line signal at a second fixed predetermined phase position.

Claim 10

The system of claim 6 wherein said first and second predetermined phase positions are of opposite polarity.

Claim 11

The system of claim 7 wherein said superimposing means are each comprised of solid state switch means and reactance means positioned between and in series with said conductor and switch means, with said solid state switch means having said reactance means as its collector load.

Claim 12

The system of claim 6 wherein said line signal is an alternating current wave and said first and second predetermined phase positions correspond with the positive and negative peak amplitudes of said line signal.

Claim 13

In a circuit system for inserting logic signals on a conductor to transmit data to a spaced location and remove such data, including: means for providing a line signal on said conductor; means for providing data logic signals to said circuit system; means for providing synchronization logic signals to said circuit system, said data logic signals being time coordinated with a first position on the line signal, said synchronization logic signal being time coordinated with a second position on the line signal which is phase spaced from said first position; means responsive to said data logic signal for superimposing a pulse on said line signal at a first predetermined phase position; means responsive to said synchronization logic signal for superimposing a pulse on said line signal at a second predetermined phase position; and means at such spaced location for rejecting said line signal and generating pure pulses corresponding with said first and second predetermined phase positions.

Claim 14

In a circuit system for inserting logic signals on a conductor to transmit data to a spaced location and remove such data, including: means for providing a line signal on said conductor; means for providing data logic signals to said circuit system; means for providing synchronization logic signals to said circuit system, said data logic signals being time coordinated with a first position on the line signal, said synchronization logic signal being time coordinated with a second position on the line signal which is phase spaced from said first position; means responsive to said data logic signal for superimposing a pulse on said line signal at a first predetermined phase position; means responsive to said synchronization logic signal for superimposing a pulse on said line signal at a second predetermined phase position; and means at such spaced location for rejecting said line signal and generating pure pulses corresponding with said first and second predetermined phase positions.

Claim 15

The system of claim 10 and further including means at such spaced location for comparing said pure pulses corresponding to said first and second predetermined phase positions with the phasE polarity of said line signal to differentiate between said pulses at said first and second positions.

Claim 16

The apparatus of claim 11 and further including means responsive to the variations of said line signal for registering and storing logic bits to corresponding to said differentiated pulses.

Claim 17

A borehole data system for transmitting logic data from a downhole location to a spaced location over a single conductor path including: downhole detecting means for determining a parameter; means for providing a line signal to said downhole detecting means via the single conductor path; means responsive to said downhole detecting means for providing a logic signal to said system; means for superimposing said logic signal on said line signal in a fixed predetermined phase relation with said line signal; and means at the spaced location for detecting said superimposed logic signal in its fixed predetermined phase relation with said line signal.

Claim 18

A borehole data system for transmitting logic data from a downhole location to a spaced location over a single conductor path including: downhole detecting means for determining a parameter; means for providing a line signal to said downhole detecting means via the single conductor path; means responsive to said downhole detecting means for providing a logic signal to said system; means for superimposing said logic signal on said line signal in a fixed predetermined phase relation with said line signal; and means at the spaced location for detecting said superimposed logic signal in its fixed predetermined phase relation with said line signal.

Claim 19

The system of claim 13 wherein said logic signal is comprised of a plurality of events, with each of said events having a predetermined phase relation.

Claim 20

The system of claim 14 wherein said detecting means at the spaced location includes clock means for separating said events according to their predetermined phase relation.

Claim 21

The system of claim 13 wherein said superimposing means includes a semiconductor arranged to provide a characteristic mark on the line signal when the semiconductor changes it conductive state.