US3648254A
Expired / Lapsed
US
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High-speed associative memory
Assignee: International Business Machines Corp
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Filing: 1969-12-31
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Granted: 1972-03-07
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Expires: 1989-12-31
Abstract
Abstract An associative search apparatus for an electronic bulk storage in which data are stored in parallel by word in a plurality of memory elements in which data bits are electronically rotatable. The memory elements are selectable by a memory selection matrix. Search tables are organized on a modular basis so that the simultaneous search of many table entries is accomplished at one time. Smaller or larger logical entries are searched within the system by executing several search operations. The first search operation marks the location of where word match conditions occurred in the first table search. The second search operation compares the second search argument against the second table only at the same relative positions where matches occurred in the first table. Marking enables any table regardless of size to be searched by using the results of a previous search operation to determine the entries to be searched on subsequent search operations.
Inventors
- 👤 William F Beausoleil
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 19:42
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
144 words
A memory for storing data at a position address, said data accessible by presenting a position address to said memory, said position address including a word position portion, said memory including a plurality of memory elements in which data bits are electronically rotatable, the improvement comprising: addressing means for decoding said position address and for selecting and energizing a first group of memory elements at a first location corresponding to said position address and a second group of memory elements corresponding to a location bearing a predetermined relationship to said first location; means for storing a search argument; means for electronically rotating data bits stored in said selected memory elements; means for reading data bits from said first and second groups of memory elements; and means responsive to said storing means and said reading means for comparing said search argument with said data bits.
Claim 2
Dependent Claim
144 words
A memory for storing data at a position address, said data accessible by presenting a position address to said memory, said position address including a word position portion, said memory including a plurality of memory elements in which data bits are electronically rotatable, the improvement comprising: addressing means for decoding said position address and for selecting and energizing a first group of memory elements at a first location corresponding to said position address and a second group of memory elements corresponding to a location bearing a predetermined relationship to said first location; means for storing a search argument; means for electronically rotating data bits stored in said selected memory elements; means for reading data bits from said first and second groups of memory elements; and means responsive to said storing means and said reading means for comparing said search argument with said data bits.
Claim 3
Dependent Claim
63 words
The combination according to claim 1 wherein said memory elements are of the type which require periodic low-speed regeneration to maintain the data stored therein; means for periodically regenerating data stored in said memory elements; and means responsive to said regeneration means for inhibiting said means for electronically rotating data bits stored in said selected memory elements for the duration of said regeneration.
Claim 4
Dependent Claim
128 words
A memory for storing data at a position address, said data accessible by presenting a position address to said memory, comprising: a plurality of memory elements in which data bits are electronically rotatable, said elements arranged in columns and rows; coordinate addressing means for decoding said position address and for energizing at least a first and a second coordinate to select a first memory element and for energizing at least a third coordinate to select a second memory element, means for storing a search argument; means for electronically rotating data bits stored in said selected memory elements; means for reading data from said first and second memory elements; and means responsive to said reading means and said storing means for comparing said search argument with said data bits.
Claim 5
Dependent Claim
128 words
A memory for storing data at a position address, said data accessible by presenting a position address to said memory, comprising: a plurality of memory elements in which data bits are electronically rotatable, said elements arranged in columns and rows; coordinate addressing means for decoding said position address and for energizing at least a first and a second coordinate to select a first memory element and for energizing at least a third coordinate to select a second memory element, means for storing a search argument; means for electronically rotating data bits stored in said selected memory elements; means for reading data from said first and second memory elements; and means responsive to said reading means and said storing means for comparing said search argument with said data bits.
Claim 6
Dependent Claim
64 words
The combination according to claim 3 wherein said memory elements are of the type which require periodic low speed regeneration to maintain the data stored therein; means for periodically regenerating data stored in said memory elements; and means responsive to said regeneration means for inhibiting said means for electronically rotating data bits stored in said selected memory elements for the duration of said regeneration.
Claim 7
Dependent Claim
163 words
A memory for storing data at a location in said memory corresponding to a position address, said data accessible by presenting a position address to said memory, comprising: a plurality of shift registers arranged in columns and rows; X-Y-addressing means for decoding said position address and for energizing a first and second X-coordinate and one Y-coordinate to select first and second shift registers at the intersection thereof; means for storing a search argument; means for electronically rotating data bits stored in said selected shift registers and for maintaining an indication of the electronic position of said data bits in said selected shift registers; means for comparing said indication of the electronic position of said data bits with said position address to thereby indicate that said data bits stored in said selected shift registers have been electronically rotated to the location in said memory corresponding to said position address, and compare logic means for comparing data stored at said location with said search argument.
Claim 8
Dependent Claim
163 words
A memory for storing data at a location in said memory corresponding to a position address, said data accessible by presenting a position address to said memory, comprising: a plurality of shift registers arranged in columns and rows; X-Y-addressing means for decoding said position address and for energizing a first and second X-coordinate and one Y-coordinate to select first and second shift registers at the intersection thereof; means for storing a search argument; means for electronically rotating data bits stored in said selected shift registers and for maintaining an indication of the electronic position of said data bits in said selected shift registers; means for comparing said indication of the electronic position of said data bits with said position address to thereby indicate that said data bits stored in said selected shift registers have been electronically rotated to the location in said memory corresponding to said position address, and compare logic means for comparing data stored at said location with said search argument.
Claim 9
Dependent Claim
32 words
The combination according to claim 5 wherein said shift registers comprise field effect transistors, connected as a dynamic shift register wherein data is stored and transferred by charging and discharging stray capacitance.
Claim 10
Dependent Claim
63 words
The combination according to claim 5 wherein said shift registers are of the type which require periodic low-speed regeneration to maintain the data stored therein; means for periodically regenerating data stored in said shift registers; and means responsive to said regeneration means for inhibiting said means for electronically rotating data bits stored in said selected shift registers for the duration of said regeneration.
Claim 11
Dependent Claim
74 words
The combination according to claim 7 wherein said regenerating means includes means for electronically rotating data bits stored in all of said shift registers at least one bit position to thereby regenerate the data stored therein; and means for maintaining an indication of the electronic position of data in all unselected shift registers, independently of said means for maintaining an indication of the electronic position of said data bits in said selected shift registers.
Claim 12
Independent Claim
117 words
The method of controlling a bulk memory of the type in which data are stored in memory elements in which data bits are electronically rotatable for searching data stored therein for datum matching a search key comprising the steps of: rotating the data bits in a set of said elements at low speed to thereby sustain data stored therein; selecting a first and a second subset of memory elements within said set; electronically rotating data bits in said selected subsets of memory elements at a rate which is independent of the rate necessary to sustain data stored in said memory; and comparing data read from said first- and second-selected subsets of memory elements with said search key.
Claim 13
Independent Claim
117 words
The method of controlling a bulk memory of the type in which data are stored in memory elements in which data bits are electronically rotatable for searching data stored therein for datum matching a search key comprising the steps of: rotating the data bits in a set of said elements at low speed to thereby sustain data stored therein; selecting a first and a second subset of memory elements within said set; electronically rotating data bits in said selected subsets of memory elements at a rate which is independent of the rate necessary to sustain data stored in said memory; and comparing data read from said first- and second-selected subsets of memory elements with said search key.
Claim 14
Dependent Claim
53 words
The method of claim 9 further comprising the steps of: selecting a marking bit memory element concurrently with said first and second subsets; and writing marking indicia into bit positions in said marking bit memory element corresponding to positions within said subsets at which data read from said subsets matches said search key.
Claim 15
Dependent Claim
98 words
For use in a bulk memory system, a modular memory plane comprising: an integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements in which data bits are electronically rotatable; X-Y-coordinate selection means for selecting within said card at least one module, and within each selected module a chip, and within said chip at least one memory element; and compare logic corresponding to each module for comparing data read from elements within each module with an external search key.
Claim 16
Dependent Claim
98 words
For use in a bulk memory system, a modular memory plane comprising: an integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements in which data bits are electronically rotatable; X-Y-coordinate selection means for selecting within said card at least one module, and within each selected module a chip, and within said chip at least one memory element; and compare logic corresponding to each module for comparing data read from elements within each module with an external search key.
Claim 17
Dependent Claim
62 words
The combination according to claim 11 further including: reading means connected to said memory elements in each module to thereby provide common data output for each element in said module; whereby when said memory elements are selected by said X- and Y-coordinates, data is read from each module and compared with said search key at said compare logic corresponding to each module.
Claim 18
Dependent Claim
180 words
A bulk memory system comprising: a first integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements in which data bits are electronically rotaTable; said first card having compare logic corresponding to each module for comparing data read from elements within each module with an external search key and for energizing a match line; a second integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements; said second card having means for reading data from a selected element, and means for writing data into said selected element; X-Y-coordinate selection means for selecting within said first and second cards at least one module, and within each selected module a chip, and within said chip at least one memory element; and means responsive to said match line at said first card or said reading means at said second card for energizing said writing means.
Claim 19
Dependent Claim
180 words
A bulk memory system comprising: a first integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements in which data bits are electronically rotaTable; said first card having compare logic corresponding to each module for comparing data read from elements within each module with an external search key and for energizing a match line; a second integrated circuit card having arranged thereon in columns and rows a plurality of modules, each module comprising a plurality of chips, each chip comprising a plurality of memory elements; said second card having means for reading data from a selected element, and means for writing data into said selected element; X-Y-coordinate selection means for selecting within said first and second cards at least one module, and within each selected module a chip, and within said chip at least one memory element; and means responsive to said match line at said first card or said reading means at said second card for energizing said writing means.
Claim 20
Dependent Claim
149 words
Auxiliary storage apparatus comprising: a plurality of multibit memory elements arranged in modules in columns and rows in memory planes, one plane for each bit position of a word; address decoding means for selecting columns and rows to thereby select at least one memory element location on each module; means for electronically rotating data stored in the selected memory elements in unison to thereby read words in parallel, each bit of a word being read from a corresponding memory plane; means for maintaining a position count of the contents of the memory elements as they are rotated; means for comparing the address of a particular word position with the state of said count means, such that when the two compare, the words corresponding to the word position address are accessible at each selected module; and means for simultaneously comparing the accessible words at each module with a search key.
Claim 21
Dependent Claim
149 words
Auxiliary storage apparatus comprising: a plurality of multibit memory elements arranged in modules in columns and rows in memory planes, one plane for each bit position of a word; address decoding means for selecting columns and rows to thereby select at least one memory element location on each module; means for electronically rotating data stored in the selected memory elements in unison to thereby read words in parallel, each bit of a word being read from a corresponding memory plane; means for maintaining a position count of the contents of the memory elements as they are rotated; means for comparing the address of a particular word position with the state of said count means, such that when the two compare, the words corresponding to the word position address are accessible at each selected module; and means for simultaneously comparing the accessible words at each module with a search key.
Claim 22
Dependent Claim
96 words
The combination according to claim 14 wherein a characteristic of the memory elements is that data are stored therein on a temporary basis and must be regenerated periodically, said apparatus further comprising: timing means including a high-speed clock operating in conjunction with a low-speed clock; means for selecting a particular memory element within a group of elements including means for rotating data stored in the selected elements at a higher speed under control of the high-speed clock and means for regenerating data stored in the remainder of the elements at slow speed by the low-speed clock.
Claim 23
Dependent Claim
85 words
The combination according to claim 15 including control means for presenting the word position address of the first word of a block of words to said comparing means so that data stored in the selected memory elements are electronically rotated at high speed until the position count matches the word position address; means for halting the rotation; and means for accessing successive words by incrementing the word position address and electronically rotating data stored in the selected memory elements one word position at a time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |