US3648180A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pulse generators
Assignee: BAC AND BRITISH AEROSPACE
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Filing: 1970-10-06
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Granted: 1972-03-07
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Expires: 1990-10-06
Abstract
Abstract The pulse generator is described in which a pair of storage registers are connected in parallel with one another and initially loaded such that a first of the registers has a substantially smaller unfilled capacity than the second register. A clock generator then feeds pulses equally to the two registers to progressively reduce the unfilled capacity of each register and when the first register has been filled a ''full'' signal is generated which causes immediate reloading of the first register to the same initial capacity. A logic circuit connected to selected bit outputs of the first register generates a pulse, or a pulse pattern, during the time taken to fill the first register and when the second register has been filled a second ''full'' signal inhibits the feeding of further clock pulses to the register. The total number of pulse cycles is therefore the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.
Inventors
- 👤 Terence Keith Woodcock
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 04:32
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03K3/00; H03K3/64; H03K3/72
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
165 words
A method of deriving a pulse train having a predetermined number of pulses comprising: initially loading a pair of storage registers such that a first of the registers has a substantially smaller unfilled capacity than the second register, feeding clock pulses equally to the two registers to progressively reduce the unfilled capacity of each register, momentarily inhibiting the feeding of clock pulses to the registers in response to the filling of the first register and immediately reloading the first register to the same initial capacity, feeding selected bit outputs of the first register to a logic circuit to generate an output pulse, or a pulse pattern, during the time taken to fill the first register, and inhibiting the feeding of further pulses to the registers in response to the filling of the second register whereby the total number of output pulses, or pulse patterns, generated is the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.
Claim 2
Independent Claim
165 words
A method of deriving a pulse train having a predetermined number of pulses comprising: initially loading a pair of storage registers such that a first of the registers has a substantially smaller unfilled capacity than the second register, feeding clock pulses equally to the two registers to progressively reduce the unfilled capacity of each register, momentarily inhibiting the feeding of clock pulses to the registers in response to the filling of the first register and immediately reloading the first register to the same initial capacity, feeding selected bit outputs of the first register to a logic circuit to generate an output pulse, or a pulse pattern, during the time taken to fill the first register, and inhibiting the feeding of further pulses to the registers in response to the filling of the second register whereby the total number of output pulses, or pulse patterns, generated is the ratio of the initially unfilled capacity of the second register to the unfilled capacity of the first register.
Claim 3
Dependent Claim
163 words
A pulse generator for generating a pulse train having a predetermined number of pulses, or pulse patterns, comprising a pair of storage registers, a clock for feeding pulses equally to the two registers, means responsive to the filling of a first of the registers for momentarily inhibiting the clock pulses to the registers and immediately reloading the first register, a logic circuit connected to selected bit outputs of the first register to generate an output pulse, or a pulse pattern, during the time taken to fill the first register, and means responsive to the filling of the second register to inhibit the feeding of further pulses to the registers, whereby, if the two registers are repeatedly loaded such that the first register has a substantially smaller unfilled capacity than the second register, the total number of output pulses, or pulse patterns generated is the ratio of the initially unfilled capacity of the second register to the initially unfilled capacity of the first register.
Claim 4
Dependent Claim
163 words
A pulse generator for generating a pulse train having a predetermined number of pulses, or pulse patterns, comprising a pair of storage registers, a clock for feeding pulses equally to the two registers, means responsive to the filling of a first of the registers for momentarily inhibiting the clock pulses to the registers and immediately reloading the first register, a logic circuit connected to selected bit outputs of the first register to generate an output pulse, or a pulse pattern, during the time taken to fill the first register, and means responsive to the filling of the second register to inhibit the feeding of further pulses to the registers, whereby, if the two registers are repeatedly loaded such that the first register has a substantially smaller unfilled capacity than the second register, the total number of output pulses, or pulse patterns generated is the ratio of the initially unfilled capacity of the second register to the initially unfilled capacity of the first register.
Claim 5
Dependent Claim
41 words
A pulse generator according to claim 2 further including a third register, so arranged that the contents of the third register are parallel loaded into the first register in response to a signal signifying that the first register hAs been filled.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-03-07 | 1975-09-06 | 1976-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-03-07 | 1979-09-06 | 1980-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-03-07 | 1983-09-06 | 1984-03-07 | $7700.00 | Window Closed / Lapsed |