Error detector circuit

Claim 2

An electronic detector circuit for receIving and testing pulse trains to determine whether they are bipolar pulse trains, comprising: means for receiving a pulse train and converting said received pulse train into two additional pulse trains of opposite polarity with respect to each other, logic means connected to respond to successive pulses of said two pulse trains to provide output signals of a particular character when the polarity of successive pulses alternate, and means responsive to the output signals to indicate when a bipolar pulse train is being received, said logic means comprising: logic elements in each of two paths, a first NOT gate in each path responsive to LOW input pulses to provide a HIGH output, a differentiator and a NOR gate coupled in each path, means coupling the differentiator to receive the HIGH output of the NOT gate and to provide differentiated signals to the corresponding NOR gate, and means coupling outputs from the NOT gate of each path and the NOR gate of each path to a NAND gate, whereby the NAND gate is energized when two HIGH pulses are received to provide a LOW signal, indicating the receipt of bipolar pulses.

Claim 3

A circuit as claimed in claim 1, in which the means responsive to the output signals to indicate when a bipolar pulse train is being received comprises: a NAND gate responsive to a LOW signal from the logic means to provide a HIGH signal, and means responsive to the HIGH signal to provide a potential sufficient to operate an indicator device.

Claim 4

A circuit as claimed in claim 1 in which the logic means includes: interconnections coupling the output of a NOR gate in a first path to the input of a NOR gate in the second path, and switching means for interconnecting the output of the NOR gate in the second path to the input of the NOR gate in the first path, said interconnections enabling the logic means to detect errors in a bipolar pulse train.

Claim 5

An electronic detector circuit for receiving and testing pulse trains to determine whether they are bipolar pulse trains, comprising: means for receiving a pulse train and converting said received pulse train into two additional pulse trains of opposite polarity with respect to each other, logical means connected to respond to successive pulses of said two pulse trains and to provide output signals of a particular character when the polarity of successive pulses alternate, and means responsive to the output signals to indicate when a bipolar pulse train is being received, and connections to enable error detection, in which the logic means comprises: logic elements in each of two paths, a NOT gate in each path responsive to LOW input pulses to provide HIGH output, a differentiator and a NOR gate coupled in each path, means coupling the differentiator to receive the HIGH output of the NOT gate and to provide differentiated signals to the corresponding NOR gate, means crosscoupling the outputs of each NOR gate to the input of the other NOR gate, and means coupling outputs from the NOT gate of each path and the NOR gate of each path to a NAND gate, whereby the NAND gate is energized when two HIGH pulses are received to provide a LOW indicating the occurrence of an error in the pulse train.

Claim 6

An electronic detector circuit for receiving and testing pulse trains to determine whether they are bipolar pulse trains, comprising: means for receiving a pulse train and converting said received pulse train into two additional pulse trains of opposite polarity with respect to each other, logical means connected to respond to successive pulses of said two pulse trains and to provide output signals of a particular character when the polarity of successive pulses alternate, and means responsive to the output signals to indicate when a bipolar pulse train is being received, and connections to enable error detection, in which the logic means comprises: logic elements in each of two paths, a NOT gate in each path responsive to LOW input pulses to provide HIGH output, a differentiator and a NOR gate coupled in each path, means coupling the differentiator to receive the HIGH output of the NOT gate and to provide differentiated signals to the corresponding NOR gate, means crosscoupling the outputs of each NOR gate to the input of the other NOR gate, and means coupling outputs from the NOT gate of each path and the NOR gate of each path to a NAND gate, whereby the NAND gate is energized when two HIGH pulses are received to provide a LOW indicating the occurrence of an error in the pulse train.