US3644901A
Expired / Lapsed
US
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Digital system for controlling signal transfers between registers and data buses
Assignee: Iowa State University of Science and Technology
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Filing: 1969-07-24
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Granted: 1972-02-22
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Expires: 1989-07-24
Abstract
Abstract The selective transfer of data signals from selected ones of a plurality of storage registers to selected ones of a separate number of data buses is achieved by storing control signals in control registers associated with each of the storage registers. The control signals indicate the data bus to which the signal contents of the storage register associated with that control register are to be transmitted; and gating circuitry responsive to the control register signals couple the signal contents of the registers to the proper data buses. The communication between registers and buses is maintained until the contents of one of the control registers is changed. Thus, a number of registers may communicate with a number of buses simultaneously; and the contents of a bus may be operated on directly. Circuitry is also disclosed for simultaneously coupling the signal contents of data buses to selected registers.
Inventors
- 👤 Roy J Zingg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 22:41
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
182 words
In a data processing system the combination comprising a plurality of data buses, each including a plurality of separate digit lines, a plurality of storage register means each capable of storing multiple binary signals, control register means associated with each of said storage register means for storing a plurality of binary signals representative of a desired transmission between the data contents one of said registers and corresponding digit lines of one of said buses, each of said control register means independently operable of the others, and a plurality of gating means, one for each of said storage registers, each receiving the signal contents of one of said register means for transmitting said binary signals respectively to said digit lines of a selected bus responsive to said signals stored in the control means associated with that register means, whereby the signal contents of more than one storage register may be selectively transmitted to separate one of said data buses or to the same data bus and the transmission will be effective until the signal contents of the activating control register means is altered.
Claim 2
Dependent Claim
182 words
In a data processing system the combination comprising a plurality of data buses, each including a plurality of separate digit lines, a plurality of storage register means each capable of storing multiple binary signals, control register means associated with each of said storage register means for storing a plurality of binary signals representative of a desired transmission between the data contents one of said registers and corresponding digit lines of one of said buses, each of said control register means independently operable of the others, and a plurality of gating means, one for each of said storage registers, each receiving the signal contents of one of said register means for transmitting said binary signals respectively to said digit lines of a selected bus responsive to said signals stored in the control means associated with that register means, whereby the signal contents of more than one storage register may be selectively transmitted to separate one of said data buses or to the same data bus and the transmission will be effective until the signal contents of the activating control register means is altered.
Claim 3
Dependent Claim
52 words
The system of claim 1 wherein said control means is responsive to command signals for communicating its associated register with a selected data bus whereby an established communication between an associated register means and said selected data bus is terminated only upon receipt of a different command signal by said control means.
Claim 4
Dependent Claim
73 words
The system of claim 1 further comprising unload control register means associated with at least one of said register means for storing signals representative of a desired communication between a selected data bus and said associated register means, and unload gate means having input buses for transmitting the data on a selected data bus to the input of said associated register means responsive to said signals stored in said unload control register means.
Claim 5
Dependent Claim
124 words
The system of claim 1 further comprising combinational logic net means including a plurality of binary signals on separate output digit lines, load control register means associated with said logic net means for storing signals representative of a desired transmission between the output digit lines of said logic net means and a predetermined data bus, and load gate means having input means connected to the digit lines of said logic net means and a plurality of output channel means each connected to the digit lines of different data buses for communicating said digit lines of said logic net means with the digit lines of a selected data bus responsive to said signals stored in said load register means associated with said logic net means.
Claim 6
Dependent Claim
101 words
In combination, a plurality of data buses, each having a number of separate lines each associated with a bit in a word, a plurality of storage register means for storing binary signals representative of a word, a control register means associated with each of said storage register means, and gating means for each of said storage register means for selectively gating the signal contents of an associated storage register to a selected one of said data buses responsive to the signal contents of the control register means associated with that storage register means from which the signal contents are being transmitted.
Claim 7
Dependent Claim
101 words
In combination, a plurality of data buses, each having a number of separate lines each associated with a bit in a word, a plurality of storage register means for storing binary signals representative of a word, a control register means associated with each of said storage register means, and gating means for each of said storage register means for selectively gating the signal contents of an associated storage register to a selected one of said data buses responsive to the signal contents of the control register means associated with that storage register means from which the signal contents are being transmitted.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1975-02-21 | 1975-08-23 | 1976-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1979-02-21 | 1979-08-23 | 1980-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1983-02-21 | 1983-08-23 | 1984-02-22 | $7700.00 | Window Closed / Lapsed |