Insulated gate field effect transistors

Claim 2

A transistor as set forth in claim 1 wherein the ohmic contact to the substrate region is made to a surface portion of the third region available to said plane surface.

Claim 3

A transistor as set forth in claim 3 wherein the ohmic contact on the third region is located on the side of the source remote from the drain.

Claim 4

A transistor as set forth in claim 3 and further including means interconnecting the ohmic contacts on the third region and on the source.

Claim 5

A transistor as set forth in claim 1 wherein the source-drain spacing is at most 5 Mu .

Claim 6

An insulated gate field effect transistor comprising a monocrystalline semiconductor substrate portion of one type conductivity having a plane surface, first and second spaced surface diffused regions of the opposite type conductivity located within the substrate portion and constituting source and drain regions, respectively, a third surface diffused region of the said one type conductivity in the substrate, said third region containing active impurities forming said one type conductivity distributed in a concentration which decreases from the plane surface into the substrate bulk and which also decreases laterally in a peripheral portion, a dielectric layer on the substrate plane surface between the source and drain regions which constitutes a channel region, a conductive layer on the dielectric layer and overlying the channel region and constituting a gate electrode, said first source region lying wholly within the third region and spaced from its lateral boundary and with the side of the source contiguous with the channel region being located within the peripheral portion of the third region of laterally decreasing impurity concentration which thereby becomes located in the channel region, said channel region thereby having adjacent the source a one type forming impurity concentration that is larger than that in the substrate portion underlying the third region and that decreases in the direction from source to drain, ohmic contacts to the source, drain, and gate, and an ohmic connection to the third region.

Claim 7

An insulated gate field effect transistor comprising a monocrystalline semiconductor body having a first portion on one type conductivity having a surface, second and third spaced regions of the body and of the opposite type conductivity constituting source and drain regions, respectively, and defining therebetween a channel region in the first portion, a fourth surface zone of the said one type condUctivity in the first body portion, said fourth zone containing active impurities forming said one type conductivity distributed in a concentration which decreases from the surface into the body portion bulk and which also decreases in a peripheral portion, a dielectric layer on the surface and over the channel region, a conductive layer on the dielectric layer and overlying the channel region and constituting a gate electrode, said second source region lying wholly within the fourth zone and spaced from its outer boundary and with the side of the source contiguous with the channel region being located within the peripheral portion of the fourth zone of decreasing impurity concentration which thereby becomes located in the channel region, said channel region thereby having adjacent the source a one type forming impurity concentration that is larger than that in the body portion underlying the fourth zone and that decreases in the direction from source to drain, and ohmic connections to the source, drain, and gate.

Claim 8

A transistor as set forth in claim 8 wherein an ohmic connection is made to a surface portion of the fourth zone available at said surface.