Linear charge redistribution pcm coder and decoder

Claim 2

In a system which utilizes analog-type signals coded as digital-type signals comprising binary words, each word being associated with an analog sample and each digit of a binary word being associated with a quantizing level of the coded analog sample, apparatus for converting signals of one type to corresponding signals of the other type comprising: a source of timing pulses; a reference voltage source; first, second, third, and fourth capacitors; means for charging said first capacitor to the reference voltage; means, under the control of the timing pulses, for establishing a step voltage waveform by periodically coupling together said first and second capacitors allowing charge to be redistributed therebetween, said second capacitor being discharged prior to each of said couplings; means for sequentially applying a voltage to said third capacitor which equals the sum of the voltage on said fourth capacitor and the voltage of said step voltage waveform; means responsive to the voltage on said third capacitor for developing an output signal; and means for charging said fourth capacitor to the voltage on said third capacitor upon occurrence of a digital signal pulse.

Claim 3

A signal converter as claimed in claim 1 wherein said means for sequentially applying a voltage to said third capacitor comprises a summing amplifier, the voltages of said step voltage waveform and on said fourth Capacitor being added by said amplifier and the sum being placed on said third capacitor.

Claim 4

A signal converter as claimed in claim 1 wherein said means for sequentially applying a voltage to said third capacitor comprises said second and fourth capacitors and buffering means, said fourth capacitor being series connected with said second capacitor and said buffering means being connected between said fourth and said third capacitors.

Claim 5

A signal converter as defined in claim 1 wherein said converter is an analog to digital converter and said means for developing an output signal includes means for emitting a digital signal pulse whenever the voltage on said third capacitor is less than or equal to the analog sample voltage.

Claim 6

A signal converter as defined in claim 1 wherein said converter is a digital to analog converter and said means for developing an output signal includes means for sampling the voltage on said third capacitor.

Claim 7

In a system which utilizes analog-type signals coded as digital-type signals comprising binary words, each word being associated with an analog sample and each digit of a binary word being associated with a quantizing level of the coded analog sample, means for converting signals of one type to corresponding signals of the other type comprising: a source of timing pulses; first, second, and third, and fourth capacitors and means for discharging them; control pulsing means, responsive to the timing pulses, for generating and transmitting control pulses at a specified rate; a reference voltage source including fifth, sixth, and seventh capacitors, a minimum and a maximum steady state voltage supply, switching means, responsive to indicating pulses, for connecting said sixth capacitor between said maximum steady state voltage supply and said fifth capacitor, switching means responsive to control pulses from said control pulsing means for connecting said seventh capacitor between said minimum steady state voltage supply and said fifth capacitor, said means for charging said first capacitor to the reference voltage including buffering means connected at its input to said fifth capacitor and at its output by said switching means to said first capacitor; means for charging said first capacitor to the reference voltage; means under the control of the timing pulses for applying to said second capacitor successively diminishing increments of the voltage on said first capacitor, preceding increments being discharged to ground by said discharging means before succeeding increments are applied; means for sequentially applying to said third capacitor the sum of the voltage on said fourth capacitor and the voltage on said first capacitor; means for charging said fourth capacitor to the voltage on said third capacitor upon occurrence of a digital signal pulse; and means, under the control of the timing pulses and responsive to the digital signals, for varying the reference voltage in accordance with the analog sample sizes including means under the control of the timing pulses for detecting a maximum binary word corresponding to the largest analog sample to be encoded, means responsive to said detecting means for signaling the detection of the maximum binary word to said reference voltage source by means of indicating pulses, said control pulsing means, and means, responsive to the indicating pulses for inhibiting the transmission of control pulses from said control pulsing means to said reference voltage source, said reference voltage source generating a reduced reference voltage upon receipt of control pulses and generating an increased reference voltage upon the receipt of indicating pulses.

Claim 8

In a system which utilizes analog-type signals coded as digital-type signals comprising binary words, each word being associated with an analog sample and each digit of a binary word being associated with a quantizing level of the coded analog sample, means for converting signals of one type to corresponding signals of the other type comprising: a source of timing pulses; first, second, and third, and fourth capacitors and means for discharging them; control pulsing means, responsive to the timing pulses, for generating and transmitting control pulses at a specified rate; a reference voltage source including fifth, sixth, and seventh capacitors, a minimum and a maximum steady state voltage supply, switching means, responsive to indicating pulses, for connecting said sixth capacitor between said maximum steady state voltage supply and said fifth capacitor, switching means responsive to control pulses from said control pulsing means for connecting said seventh capacitor between said minimum steady state voltage supply and said fifth capacitor, said means for charging said first capacitor to the reference voltage including buffering means connected at its input to said fifth capacitor and at its output by said switching means to said first capacitor; means for charging said first capacitor to the reference voltage; means under the control of the timing pulses for applying to said second capacitor successively diminishing increments of the voltage on said first capacitor, preceding increments being discharged to ground by said discharging means before succeeding increments are applied; means for sequentially applying to said third capacitor the sum of the voltage on said fourth capacitor and the voltage on said first capacitor; means for charging said fourth capacitor to the voltage on said third capacitor upon occurrence of a digital signal pulse; and means, under the control of the timing pulses and responsive to the digital signals, for varying the reference voltage in accordance with the analog sample sizes including means under the control of the timing pulses for detecting a maximum binary word corresponding to the largest analog sample to be encoded, means responsive to said detecting means for signaling the detection of the maximum binary word to said reference voltage source by means of indicating pulses, said control pulsing means, and means, responsive to the indicating pulses for inhibiting the transmission of control pulses from said control pulsing means to said reference voltage source, said reference voltage source generating a reduced reference voltage upon receipt of control pulses and generating an increased reference voltage upon the receipt of indicating pulses.