Clocked set-reset flip-flop

Claim 2

In combination: a flip-flop; first means connected to said flip-flop for periodically changing the state of said flip-flop in response to periodic clock pulses; second means connected to said flip-flop for setting and resetting said flip-flop in response to set and reset pulses, respectively; and third means connected to said flip-flop and to said first means and said second means for preventing the changing of state of said flip-flop in response to a clock pulse which is applied concurrently with one of said set and reset pulses, and which clock pulse tends to change the flip-flop to a state different than that intended by said one of said set and reset pulses.

Claim 3

In combination: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating set and reset pulses; means for generating two sets of clock pulses, one complementary to the other first and second transmission gates each having input and output terminals and a control terminal, the input terminal of the first being connected to said reset terminal and the output terminal of the first being connected to said first charge storage, the input terminal of the second being connected to said set terminal and the output terminal of the second being connected to said second charge storage means, and the control terminal of each gate being connected to the means for generating said first set of clock pulses; third and fourth transmission gates each having input and output terminals and a control terminal, the input terminal of the third being connected to the output terminal of said first transmission gate and said first charge storage means, the control terminal of the third being connected to said means for generating set pulses, the input terminal of the fourth being connected to the output terminal of said second gate and said second charge storage means, the output terminal of said third and fourth gate being connected to the means for generating said first set of clock pulses; a current source; first and second field effect transistors each having input, output, and control electrodes, the output electrode of the first being connected to the input electrode of the second, the input electrode of the first being connected to said current source, the control electrode of the first being connected to said means for generating said second set of clock pulses, and the output electrode of the second being connected to said reset terminal and the control electrode of the second being connected to said first charge storage means; and third and fourth field effect transistors each having input, output, and control electrodes, the output electrode of the third being connected to the input electrode of the fourth, the input electrode of the third being connected to said current source, the control electrode of the third being connected to said means for generating said second set of clock pulses, and the output electrode of the fourth being connected to said set terminal and the control electrode of the fourth being connected to said second charge storage means.

Claim 4

In combination: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating set and reset pulses; means for generating two sets of clock pulses, one complementary to the other first and second transmission gates each having input and output terminals and a control terminal, the input terminal of the first being connected to said reset terminal and the output terminal of the first being connected to said first charge storage, the input terminal of the second being connected to said set terminal and the output terminal of the second being connected to said second charge storage means, and the control terminal of each gate being connected to the means for generating said first set of clock pulses; third and fourth transmission gates each having input and output terminals and a control terminal, the input terminal of the third being connected to the output terminal of said first transmission gate and said first charge storage means, the control terminal of the third being connected to said means for generating set pulses, the input terminal of the fourth being connected to the output terminal of said second gate and said second charge storage means, the output terminal of said third and fourth gate being connected to the means for generating said first set of clock pulses; a current source; first and second field effect transistors each having input, output, and control electrodes, the output electrode of the first being connected to the input electrode of the second, the input electrode of the first being connected to said current source, the control electrode of the first being connected to said means for generating said second set of clock pulses, and the output electrode of the second being connected to said reset terminal and the control electrode of the second being connected to said first charge storage means; and third and fourth field effect transistors each having input, output, and control electrodes, the output electrode of the third being connected to the input electrode of the fourth, the input electrode of the third being connected to said current source, the control electrode of the third being connected to said means for generating said second set of clock pulses, and the output electrode of the fourth being connected to said set terminal and the control electrode of the fourth being connected to said second charge storage means.

Claim 5

In the combination as set forth in claim 2, said last-named means comprising: a two input terminal logic gate, a charge storage element coupled to one input terminal of said gate for priming said gate, when charged said other input terminal comprising a clock pulse terminal to which said clock pulses are applied for enabling said gate when said capacitor is charged; and means responsive to said one of said set and reset pulses for discharging said charge storage element.

Claim 6

In combination: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating first and second sets of clock pulses which are complementary to each other; means connected to receive and be responsive to said first set of clock pulses to selectively provide a circuit path for charging said first and second charge storage means to the voltages at said set and reset terminals, respectively; means connected to receive and be responsive to the concurrent application of a set pulse and a pulse in said first set of clock pulses to selectively provide a circuit path for discharging said first charge storage means; means connected to receive and be responsive to the concurrent application of a reset pulse and a pulse in said first set of clock pulses to selectively provide a circuit path for discharging said second charge storage means; and means for applying a pulse to one of said set and reset terminals for changing the state of said flip-flop in response to one of said charge storage means being charged concurrent with the production of a pulse in said second set of clock pulses.

Claim 7

In combination: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating first and second sets of clock pulses which are complementary to each other; means connected to receive and be responsive to said first set of clock pulses to selectively provide a circuit path for charging said first and second charge storage means to the voltages at said set and reset terminals, respectively; means connected to receive and be responsive to the concurrent application of a set pulse and a pulse in said first set of clock pulses to selectively provide a circuit path for discharging said first charge storage means; means connected to receive and be responsive to the concurrent application of a reset pulse and a pulse in said first set of clock pulses to selectively provide a circuit path for discharging said second charge storage means; and means for applying a pulse to one of said set and reset terminals for changing the state of said flip-flop in response to one of said charge storage means being charged concurrent with the production of a pulse in said second set of clock pulses.

Claim 8

The combination claimed in claim 4 said means responsive to said first set of clock pulses for charging said first and second charge storage means comprising first and second switches each having an input terminal, an output terminal and a control terminal, the input terminal of the first being connected to the reset terminal and the output terminal to said first charge storage means, and the input terminal of the second being connected to the set terminal and the output terminal being connected to said second charge storage means, the control terminal of each switch being responsive to said first set of clock pulses.

Claim 9

The combination claimed in claim 5 said means responsive to the application to said set terminal of a set pulse concurrently with the production of a pulse in said first set of clock pulses for discharging said first charge storage means comprising a field effect transistor having an input electrode, an output electrode and a control electrode, the input electrode being connected to said first charge storage means and the output electrode being connected to the means for generating said first set of clock pulses, and the control terminal being responSive to said set pulse.

Claim 10

The combination claimed in claim 6 said means responsive to the application to said reset terminal of a reset pulse concurrently with the production of a pulse in said first set of clock pulses for discharging said second charge storage means comprising a field effect transistor having an input electrode, an output electrode, and a control electrode, the input electrode being connected to said second charge storage means, and the output electrode being connected to the means for generating said first set of clock pulses, and the control terminal being responsive to said reset pulse.

Claim 11

The combination claimed in claim 7 the means for applying a pulse to one of said terminals for changing the state of said flip-flop comprising first and second gates each having two input terminals and an output terminal, one input terminal of each gate being connected to the means for generating said second set of clock pulses, the other input terminal of the first gate being connected to said first charge storage means and the output terminal of the first gate being connected to said reset terminal, the other input terminal of the second gate being connected to said second charge storage means and the output terminal of the second gate being connected to said set terminal.

Claim 12

In a system wherein a binary ''''1'''' is represented by a signal or level of V1 volts and a binary ''''0'''' is represented by a signal or level of V0 volts, where V0 V1, the combination comprising: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating set and reset pulses; means for generating two sets of clock pulses, one complementary to the other, that is, when the first set is at a level V1 and the second set is at a level V0 and vice versa; first and second gates each having first and second input terminals and an output terminal at which a signal level V0 is produced when both the input terminals are at a level V1, the first input terminal of each gate being connected to said means for generating said second set of clock pulses, the second input terminal of the first gate being connected to said first charge storage and the output terminal of the first gate being connected to said reset terminal, and the second input terminal of said second gate being connected to said second charge storage means and the output terminal of said second gate being connected to said set terminal; means for charging said first and second charge storage means to the levels at said reset and set terminals, respectively, each time a clock pulse in said first set is at a level V1; means for discharging said first charge storage means in response to said set pulse being at a level V1 concurrent with a pulse from said first set of clock pulses being at a level V0; and means for discharging said second charge means in response to said reset pulse being at a level V1 concurrent with a pulse from said first set of clock pulses being at a level V0.

Claim 13

In a system wherein a binary ''''1'''' is represented by a signal or level of V1 volts and a binary ''''0'''' is represented by a signal or level of V0 volts, where V0 V1, the combination comprising: a flip-flop having set and reset terminals to which pulses may be applied for changing the state of said flip-flop; first and second charge storage means; means for generating set and reset pulses; means for generating two sets of clock pulses, one complementary to the other, that is, when the first set is at a level V1 and the second set is at a level V0 and vice versa; first and second gates each having first and second input terminals and an output terminal at which a signal level V0 is produced when both the input terminals are at a level V1, the first input terminal of each gate being connected to said means for generating said second set of clock pulses, the second input terminal of the first gate being connected to said first charge storage and the output terminal of the first gate being connected to said reset terminal, and the second input terminal of said second gate being connected to said second charge storage means and the output terminal of said second gate being connected to said set terminal; means for charging said first and second charge storage means to the levels at said reset and set terminals, respectively, each time a clock pulse in said first set is at a level V1; means for discharging said first charge storage means in response to said set pulse being at a level V1 concurrent with a pulse from said first set of clock pulses being at a level V0; and means for discharging said second charge means in response to said reset pulse being at a level V1 concurrent with a pulse from said first set of clock pulses being at a level V0.

Claim 14

In combination: a flip-flop having clock pulse input terminals to which clock pulses may be applied for changing the state of the flip-flop and set and reset pulse input terminals to which set and reset pulses may be applied for setting and resetting said flip-flop; means for applying successive clock pulses to said clock pulse input terminals for successively changing the state of said flip-flop; means for applying set and reset pulses to said set and reset terminals for setting and resetting said flip-flop respectively; and means responsive to the concurrent application of a clock pulse which tends to place the flip-flop in one state and to a set or reset pulse which tends to place the flip-flop in its other state for inhibiting the effect of said clock pulse and thereby placing the flip-flop in the state called for by said set or reset pulse.

Claim 15

In combination: a flip-flop having clock pulse input terminals to which clock pulses may be applied for changing the state of the flip-flop and set and reset pulse input terminals to which set and reset pulses may be applied for setting and resetting said flip-flop; means for applying successive clock pulses to said clock pulse input terminals for successively changing the state of said flip-flop; means for applying set and reset pulses to said set and reset terminals for setting and resetting said flip-flop respectively; and means responsive to the concurrent application of a clock pulse which tends to place the flip-flop in one state and to a set or reset pulse which tends to place the flip-flop in its other state for inhibiting the effect of said clock pulse and thereby placing the flip-flop in the state called for by said set or reset pulse.