Balanced optically settable memory cell

Claim 2

An optically settable memory cell, comprising first and second IGFET transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistor having a gate cross coupled to the drain of the other transistor, and each transistor having a drain extending over an area of said substrate to form a photodiode, means to couple a first potential to the drains of said first and second transistors, means to apply a second potential of the same polarity to the sources of said transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential, means to interrupt the application of said first potential to said drains and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and means to discontinue the application of said second potential to said sources and to restore said first potential to said drains, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

Claim 3

A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of the first and second transistors includes the source-drain paths of third and fourth transistors, respectively.

Claim 4

A memory cell as defined in claim 2, and in addition, digit lines connecting said first potential source through said third and fourth transistors to said first and second transistors, and word lines connected to the gates of said third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a ''''1'''' or ''''0'''' information bit.

Claim 5

A memory cell as defined in claim 1, and in addition, ''''1'''' and ''''0'''' digit lines connected through the source-drain paths of respective third and fourth transistors to the drains of said first and second transistors, and ''''1'''' and ''''0'''' word lines connected to gates of respective third and fourth transistors, whereby to render one or the other of said first and second transistors conductive for the storage of a ''''1'''' or ''''0'''' information bit.

Claim 6

A memory cell as defined in claim 4 wherein said means to couple a first potential to the drains of said first and second transistors includes fifth and sixth load impedance transistors, respectively.

Claim 7

A memory cell as defined in claim 1 wherein said means to couple a first potential to the drains of said first and second transistors includes two load impedance transistors.

Claim 8

An electrically and optically settable memory cell, comprising first and second MOS transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistors having a gate cross coupled to the drain of the other transistor to provide a bistable circuit, and each transistor having a drain extending over an area of said substrate to form a photodiode, load impedance transistors coupling a first potential to the drains of said first aNd second transistors, electrical signal input means including digit lines, word lines and third and fourth transistors to render one or the other of said first and second transistors conductive for the storage of an information bit, means to apply a second potential of the same polarity to the sources of said first and second transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential, means to disconnect said first potential from said transistor impedance means and thereby interrupt the application of the first potential to the drains of said first and second transistors, and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and means to discontinue the application of said second potential to the sources of said first and second transistors and to restore said first potential through the load impedance transistors to the drains of the first and second transistors, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.

Claim 9

An electrically and optically settable memory cell, comprising first and second MOS transistors having a substrate of one conductivity type, and each having a source and a drain of the opposite conductivity type, each transistors having a gate cross coupled to the drain of the other transistor to provide a bistable circuit, and each transistor having a drain extending over an area of said substrate to form a photodiode, load impedance transistors coupling a first potential to the drains of said first aNd second transistors, electrical signal input means including digit lines, word lines and third and fourth transistors to render one or the other of said first and second transistors conductive for the storage of an information bit, means to apply a second potential of the same polarity to the sources of said first and second transistors to render both transistors nonconductive and to charge both photodiodes to the same reverse bias potential, means to disconnect said first potential from said transistor impedance means and thereby interrupt the application of the first potential to the drains of said first and second transistors, and to apply a differential input light signal to said photodiodes to cause an unequal discharging of said photodiodes, and means to discontinue the application of said second potential to the sources of said first and second transistors and to restore said first potential through the load impedance transistors to the drains of the first and second transistors, whereby the transistor having its gate connected to the photodiode having the greater charge is rendered conductive, and the transistors then store an optically determined information bit.