US3623022A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiplexing system for interleaving operations of a processing unit
Assignee: International Business Machines Corp
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Filing: 1969-12-29
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Granted: 1971-11-23
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Expires: 1989-12-29
Abstract
Abstract Apparatus for controlling the operation of a plurality of data storage devices and the transfer of data between the devices and one or more data processing systems. The apparatus includes complete primary and partially duplicative secondary circuitry which responds to certain combinations of instructions from separate sources in the same data processing system or from different data processing systems to selectively run a primary operation at full speed or interleave a primary operation and a secondary operation.
Inventors
- 👤 Robert C Day
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-22 16:58
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F13/1605; G06F13/161; G06F1/00; G06F1/04; G06F9/00; G06F9/06; G06F9/46; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
370 words
Apparatus for controlling the operation of a plurality of data storage devices under the command of instructions from a central processing system to transfer data therebetween comprising data storage control apparatus connected to said control central processing system and adapted to communicate therewith, and connected to said plurality of data storage devices and adapted to communicate with and control the operation of any one of said data storage devices at any one time, with the improvement thereto comprising: memory means for storing information; primary memory address register means for storing primary memory address signals; secondary memory address register means for storing secondary memory address signals; primary address control means for controlling the timing of the transmission of said primary memory address signals from said primary memory address register means; secondary address control means for controlling the timing of the transmission of said secondary memory address signals from said secondary memory address register means; memory addressing means responsive to address signals transmitted from said memory address register means to address portions of said memory means; memory output means for reading information from said address portions of said memory means; decoding and control means for supplying various control signals in response to certain of said information at said memory output means; operation means responsive to certain of said control signals for selectively routing the transmission of information in said apparatus, and to and from said central processing system and said data storage devices; logic means responsive to certain of said control signals and certain of said information transmitted thereto by said operation means to supply address signals to said memory address register means; a source of clock signals; and interleave control means coupled to said primary and said secondary address control means and responsive to said source of clock signals and to certain of said control signals for selectively switching between two states of output, one state comprising supplying two separate trains of alternately occuring clock signals to, respectively, said primary and said secondary address control means, and the other state comprising supplying a single, combined train of clock signals to said primary address control means, each said supplied clock signal thereby operating said address control means to which it is supplied.
Claim 2
Dependent Claim
370 words
Apparatus for controlling the operation of a plurality of data storage devices under the command of instructions from a central processing system to transfer data therebetween comprising data storage control apparatus connected to said control central processing system and adapted to communicate therewith, and connected to said plurality of data storage devices and adapted to communicate with and control the operation of any one of said data storage devices at any one time, with the improvement thereto comprising: memory means for storing information; primary memory address register means for storing primary memory address signals; secondary memory address register means for storing secondary memory address signals; primary address control means for controlling the timing of the transmission of said primary memory address signals from said primary memory address register means; secondary address control means for controlling the timing of the transmission of said secondary memory address signals from said secondary memory address register means; memory addressing means responsive to address signals transmitted from said memory address register means to address portions of said memory means; memory output means for reading information from said address portions of said memory means; decoding and control means for supplying various control signals in response to certain of said information at said memory output means; operation means responsive to certain of said control signals for selectively routing the transmission of information in said apparatus, and to and from said central processing system and said data storage devices; logic means responsive to certain of said control signals and certain of said information transmitted thereto by said operation means to supply address signals to said memory address register means; a source of clock signals; and interleave control means coupled to said primary and said secondary address control means and responsive to said source of clock signals and to certain of said control signals for selectively switching between two states of output, one state comprising supplying two separate trains of alternately occuring clock signals to, respectively, said primary and said secondary address control means, and the other state comprising supplying a single, combined train of clock signals to said primary address control means, each said supplied clock signal thereby operating said address control means to which it is supplied.
Claim 3
Dependent Claim
75 words
The apparatus of claim 1 wherein said decoding and control means is additionally responsive to said source of clock signals to limit the duration of said control signals, thereby separating the operation of said operation means into distinct cycles, each cycle of operation being in accordance with said instruction information as addressed under the control of a single operation of said primary or said secondary address control means as determined by said interleave control means.
Claim 4
Dependent Claim
84 words
The apparatus of claim 2 wherein said information stored in said memory means includes instruction information for operating said decoding and control means, said instruction information including primary instruction information addressable from said primary memory address register means, and secondary instruction information addressable from said secondary memory address register means, whereby control signals are supplied by said decoding and control means in accordance with said primary or said secondary instruction information at each said cycle of operation as determined by said interleave control means.
Claim 5
Dependent Claim
81 words
The apparatus of claim 3 wherein said operation means includes means for communication with said data storage devices and means for communication with said central processing system, said decoding and control means supplying control signals to operate said means for communication with said data storage devices in response to certain of said supplied primary instruction information and supplying control signals to operate said means for communication with said central processing unit in response to certain of said supplied secondary instruction information.
Claim 6
Dependent Claim
71 words
The apparatus of claim 4 wherein said interleave control means additionally includes latch means responsive to one of said certain control signals to assume a first state, enabling said interleave control means to supply said two separate trains of alternately occurring clock signals, and responsive to another of said certain control signals to assume a second state, operating said interleave control means to supply said single, combined train of clock signals.
Claim 7
Dependent Claim
38 words
The apparatus of claim 5 wherein said decoding and control means comprise means responsive to certain of said primary instruction information for supplying said one and said another of said certain control signals at said memory output means.
Claim 8
Dependent Claim
30 words
The apparatus of claim 6 wherein said information stored in said memory means additionally includes supervisory instruction information addressable from either said primary or said secondary address memory register means.
Claim 9
Dependent Claim
125 words
The apparatus of claim 7 wherein interleave control means additionally includes: second latch means responsive to a third of said certain control signals to assume a first state, providing an output signal, and responsive to a fourth of said certain control signals to assume a second state, terminating said output signal; and coincidence means responsive to the coincidence of the output of said first latch means when in said first state and said output signal from said second latch means when in said first state to operate said interleave control means to supply said two separate trains of alternately occurring clock signals, and responsive to the absence of said coincidence to operate said interleave control means to supply said single, combined train of clock signals.
Claim 10
Dependent Claim
38 words
The apparatus of claim 8 where said decoding and control means include means responsive to certain of said supervisory instruction information for supplying said third and said fourth of said certain control signals at said memory output means.
Claim 11
Dependent Claim
112 words
The apparatus of claim 9 wherein: said source of said clock signals supplies said two separate trains of alternately occurring clock signals to said interleave control means; and said interleave control means includes means to continually supply one of said trains of clock signals to said primary address control means, and includes gating means operated by said coincidence means upon said coincidence of outputs to transmit the other of said trains of clock signals to said secondary address control means, and operated upon said absence of said coincidence to transmit the other of said trains of clock signals to said primary address control means, thereby combining said two trains of clock signals.
Claim 12
Dependent Claim
28 words
The apparatus of claim 9 wherein said information stored in said memory means additionally includes data information addressable from either said primary or said secondary address register means.
Claim 13
Dependent Claim
108 words
The apparatus of claim 11 further including gating means coupled to said primary and said secondary address register means for gating address signals for addressing said data information, said address signals being for simultaneous storage in said primary and said secondary memory address means, said instruction information in said primary and said secondary address control means being capable of supplying all said address signals from said primary and said secondary address register means to said memory addressing means, and said decoding and control means additionally including means for separating said addressed data information from said instruction information, whereby said data may be selectively routed by said operation means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-11-22 | 1975-05-24 | 1975-11-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-11-22 | 1979-05-24 | 1979-11-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-11-22 | 1983-05-24 | 1983-11-23 | $7700.00 | Window Closed / Lapsed |