Programmed time-out monitoring arrangement using map timing

Claim 3

The method in accordance with claim 1 in which said indication-erasing step comprises the substeps of translating an identification number for a circuit, upon which said second signal event has occurred, into a corresponding word and bit location in said memory sectors, fetching information stored at said word location in said first sector, providing a mask with only a single bit of a predetermined bit type, performing a logical AND operation with said mask and said information, replacing said information in aid first sector, and repeating said fetching, mask-providing, and AND-performing substeps for information stored in each other one of said memory sectors.

Claim 4

The method in accordance with claim 1 in which said request indicating step comprises the substeps of translating an identification number for a circuit to be monitored into a corresponding word and bit location in said memory sectors, fetching information stored at said word location in said first sector, providing a mask with only a single bit of a predetermined bit type in said bit location, and insertion-masking said information into said first sector using said mask to set said bit type in said bit location without disturbing the remainder of said information.

Claim 5

The method in accordance with claim 1 in which said steering step comprises the substeps of providing a program pointer for indicating to which of said sectors timing requests are to be steered, cyclically changing said pointer to indicate different ones of said sectors in a predetermined sequence of sectors, fetching from a sector indicated by said pointer all information stored therein in a predetermined sequence of memory words, and for each of said words, identifying the position therein of any bits indicating the presence of a timing request.

Claim 8

In combination, a pair of memory means for receiving timing status indications for determining whether or not a predetermined function is completed within at least a predetermined minimum timeout period, and means switching the memory means of said pair to receive, in an alternating sequence, said status indications, said switching means including timing means for actuating said switching means so that each memory means receives said indications in each of its status-indication-receiving parts of said sequence for an interval of duration which is substantially the same as said perIod.

Claim 9

In combination, a pair of memory means for receiving timing status indications for determining whether or not a predetermined function is completed within at least a predetermined minimum timeout period, and means switching the memory means of said pair to receive, in an alternating sequence, said status indications, said switching means including timing means for actuating said switching means so that each memory means receives said indications in each of its status-indication-receiving parts of said sequence for an interval of duration which is substantially the same as said perIod.

Claim 10

In combination, a plurality of communication lines, for each of which lines there is to be independently indicated following the occurrence of a first signal a timeout of at least a predetermined minimum duration in the absence of the occurrence of a second signal, memory means having plural sectors each including a different bit storage location corresponding to each one of said lines for storing a binary coded signal bit indication of predetermined status information about such line, means switching said sectors in recurring sequence to receive said status information from said lines, the period between such switching operations being equal to said minimum duration, means responsive to said first signal on one of said lines for causing the corresponding bit location for such line in a receiving one of said sectors to be set to a first binary code state, means thereafter responsive to occurrence of said second signal on said one line, before timeout and before the next subsequent sector switching in said sequence, resetting to a second binary state said corresponding bit for such line, and means actuatable at the end of each said period for scanning the next one of said sectors in said recurring sequence to detect every one of the bit locations of such sector which is still in said first state, and said scanning means including means for resetting all of the last-mentioned detected bit locations prior to reception of said status information in said next one of said sectors.

Claim 11

In combination, a plurality of communication lines, for each of which lines there is to be independently indicated following the occurrence of a first signal a timeout of at least a predetermined minimum duration in the absence of the occurrence of a second signal, memory means having plural sectors each including a different bit storage location corresponding to each one of said lines for storing a binary coded signal bit indication of predetermined status information about such line, means switching said sectors in recurring sequence to receive said status information from said lines, the period between such switching operations being equal to said minimum duration, means responsive to said first signal on one of said lines for causing the corresponding bit location for such line in a receiving one of said sectors to be set to a first binary code state, means thereafter responsive to occurrence of said second signal on said one line, before timeout and before the next subsequent sector switching in said sequence, resetting to a second binary state said corresponding bit for such line, and means actuatable at the end of each said period for scanning the next one of said sectors in said recurring sequence to detect every one of the bit locations of such sector which is still in said first state, and said scanning means including means for resetting all of the last-mentioned detected bit locations prior to reception of said status information in said next one of said sectors.

Claim 12

The combination in accordance with claim 7 in which said scanning means includes means initiating a communication-line service function for a line corresponding to a bit location reset by said scanning means.

Claim 13

The combination in accordance with claim 7 in which said memory means includes two of said memory sectors, and said switching means includes means switching said two sectors in alternation to receive said status information.

Claim 14

The combination in accordance with claim 7 in which said communication lines are data-transmission lines each having a plurality of data stations coupled thereto, a data control station is provided for supervising communication among said stations on any one of said lines and among said lines, and said control station includes, means interrogating said stations individually, as to the readiness of such station to communicate, by applying said first signal to such line, and each of said stations including means normally responsive within only a part of said timeout duration for applying said second signal to such line.

Claim 15

The combination in accordance with claim 7 in which said bit-resetting means comprises means resetting to said second state such bit location in said receiving sector and in all other of said sectors.