Memory control system

Claim 2

In a data processor having a central processing unit, a main memory unit and a memory controller which is interposed between said central processing unit and said main memory unit to store a portion of information from said main memory unit and simultaneously to exchange information with said central processing unit, said memory controller comprising a memory controller for the exclusive use of instruction information and a memory controller for the exclusive use of operand information.

Claim 3

In a data processor having a central processing unit, a main memory unit for storing information at every given number of bits and a memory controller, said central processing unit including at least an operand address bus for exclusively transmitting an operand address, an operand fetch bus for fetching information specified by an operand address transmitted via said operand address bus, an instruction address bus for exclusively transmitting an instruction address, and an instruction fetch bus for fetching information specified by an instruction address transmitted via said instruction address bus, said memory controller comprising a first means which operates associated with said operand address bus and said operand fetch bus and a second means which operates associated with said instruction address bus and said instruction fetch bus, and said first and second means respectively comprising: a buffer memory means for storing a plurality of information of the given number of bits, a register means for storing an address of information stored in said buffer memory means, search means for searching the existence of an address in said register means which coincides with a corresponding address transmitted via a corresponding address bus of said central processing unit to generate a coincidence signal if there exists a coincident address or to geNerate an anticoincidence signal if there exists none, means for reading out information specified by the coincident address from said buffer memory means when said search means generates a coincidence signal and transferring the readout information to said central processing unit via a corresponding fetch bus of said central processing unit, and means for reading out from said main memory unit information of the given number of bits which is specified by a part of an address which is transferred to said main memory unit when said search means generates an anticoincidence signal, for storing the readout information in said buffer memory means, for selecting sole information specified by the address out of information of the given number of bits which is read out of said main memory unit, and for transferring the selected information to said central processing unit via a corresponding fetch bus of said central processing unit.

Claim 4

In a data processor having a central processing unit, a main memory unit for storing information at every given number of bits and a memory controller, said central processing unit including at least an operand address bus for exclusively transmitting an operand address, an operand fetch bus for fetching information specified by an operand address transmitted via said operand address bus, an instruction address bus for exclusively transmitting an instruction address, and an instruction fetch bus for fetching information specified by an instruction address transmitted via said instruction address bus, said memory controller comprising a first means which operates associated with said operand address bus and said operand fetch bus and a second means which operates associated with said instruction address bus and said instruction fetch bus, and said first and second means respectively comprising: a buffer memory means for storing a plurality of information of the given number of bits, a register means for storing an address of information stored in said buffer memory means, search means for searching the existence of an address in said register means which coincides with a corresponding address transmitted via a corresponding address bus of said central processing unit to generate a coincidence signal if there exists a coincident address or to geNerate an anticoincidence signal if there exists none, means for reading out information specified by the coincident address from said buffer memory means when said search means generates a coincidence signal and transferring the readout information to said central processing unit via a corresponding fetch bus of said central processing unit, and means for reading out from said main memory unit information of the given number of bits which is specified by a part of an address which is transferred to said main memory unit when said search means generates an anticoincidence signal, for storing the readout information in said buffer memory means, for selecting sole information specified by the address out of information of the given number of bits which is read out of said main memory unit, and for transferring the selected information to said central processing unit via a corresponding fetch bus of said central processing unit.

Claim 5

In a data processor having a central processing unit, a main memory unit for storing information at every given number of bits and a memory controller, said central processing unit including at least an operand address bus for exclusively transmitting an operand address, an operand fetch bus for fetching information specified by an operand address transmitted via said operand address bus, an instruction address bus for exclusively transmitting an instruction address, and an instruction fetch bus for fetching information specified by an instruction address transmitted via said instruction address bus, said memory controller comprising a first means which operates associated with said operand address bus and said operand fetch bus and a second means which operates associated with said instruction address bus and said instruction fetch bus, and said first and second means respectively comprising: at least a first and a second buffer memory means for storing a plurality of information of the given number of bits which is read out from said main memory unit, a first and a second register means for storing addresses of information stored in said first and second buffer memory means, respectively, search means for searching the existence of an address in said first and second register means which coincides with a corresponding address transmitted via a corresponding address bus of said central processing unit to generate a coincidence signal if there exists a coincident address in at least one of said first and second register means or to generate an anticoincidence signal if there exists none, means for reading out information specified by the coincident address from a buffer memory means corresponding to a register means containing the coincident address when said search means generates a coincidence signal and transferring the readout information to said central processing unit via a corresponding fetch bus of said central processing unit, and means for reading out from said main memory unit information of the given number of bits which is specified by a part of an address which is transferred to said main memory unit when said search means generates an anti-coincidence signal, for storing the readout information in one of said first and second buffer memory means, for selecting sole information specified by the address out of information of the given number of bits which is read out of said main memory unit, and for transferring the selected information to said central processing unit via a corresponding fetch bus of said central processing unit.

Claim 6

In a data processor having a central processing unit, a main memory unit for storing information at every given number of bits and a memory controller, said central processing unit including at least an operand address bus for exclusively transmitting an operand address, an operand fetch bus for fetching information specified by an operand address transmitted via said operand address bus, an instruction address bus for exclusively transmitting an instruction address, and an instruction fetch bus for fetching information specified by an instruction address transmitted via said instruction address bus, said memory controller comprising a first means which operates associated with said operand address bus and said operand fetch bus and a second means which operates associated with said instruction address bus and said instruction fetch bus, and said first and second means respectively comprising: at least a first and a second buffer memory means for storing a plurality of information of the given number of bits which is read out from said main memory unit, a first and a second register means for storing addresses of information stored in said first and second buffer memory means, respectively, search means for searching the existence of an address in said first and second register means which coincides with a corresponding address transmitted via a corresponding address bus of said central processing unit to generate a coincidence signal if there exists a coincident address in at least one of said first and second register means or to generate an anticoincidence signal if there exists none, means for reading out information specified by the coincident address from a buffer memory means corresponding to a register means containing the coincident address when said search means generates a coincidence signal and transferring the readout information to said central processing unit via a corresponding fetch bus of said central processing unit, and means for reading out from said main memory unit information of the given number of bits which is specified by a part of an address which is transferred to said main memory unit when said search means generates an anti-coincidence signal, for storing the readout information in one of said first and second buffer memory means, for selecting sole information specified by the address out of information of the given number of bits which is read out of said main memory unit, and for transferring the selected information to said central processing unit via a corresponding fetch bus of said central processing unit.

Claim 7

A data processing system comprising: a main memory unit; a central processing unit; a common memory controller interconnected between said main memory unit and said central processing unit; and a special memory controller interconnected between said common memory controller and said central processing unit, said special memory controller including at least one instruction memory controller and at least one operand memory controller for the exclusive conTrol of instruction and operand data respectively, and wherein each of said instruction and operand memory controllers has a buffer memory associated therewith.

Claim 8

A data processing system comprising: a main memory unit; a central processing unit; a common memory controller interconnected between said main memory unit and said central processing unit; and a special memory controller interconnected between said common memory controller and said central processing unit, said special memory controller including at least one instruction memory controller and at least one operand memory controller for the exclusive conTrol of instruction and operand data respectively, and wherein each of said instruction and operand memory controllers has a buffer memory associated therewith.

Claim 9

A system according to claim 4, wherein each of said instruction memory controllers and operand memory controllers comprises a set of associative registers for receiving a predetermined number of bits corresponding to a portion of address data, a comparator circuit responsive to the contents of each of said associative registers in said set of associative registers for generating an output when the contents of first prescribed bit positions of said registers have first predetermined values; and a coincidence circuit, responsive to the output of said comparator, for generating a coincidence signal, when said predetermined values correspond to second prescribed values of second prescribed bit positions of said address data.

Claim 10

A system according to claim 5, wherein each of said memory controllers further includes a set of valid-invalid registers for receiving said predetermined number of bits corresponding to said address data portion; a selector circuit for receiving the contents of each valid-invalid register in said set of valid-invalid registers and selecting the contents of one of said registers in response to the data contents of said address data portions; means for decoding a third predetermined number of bits of said address data and for generating a decoded output signal representative thereof; and a validity data comparator, responsive to the output of said selector and said decoding means for generating a valid address indication signal, representative of the selection of a valid address in said buffer memory corresponding to said address data.

Claim 11

A system according to claim 6, further comprising a control means, responsive to a first output of said coincidence circuit and said validity data comparator for enabling the transfer of data from said main memory unit over a first data supply line to said central processing unit and for transferring data to a buffer data register associated with said buffer memory from said main memory, when either said coincidence circuit or valid data comparator supplies an output different from said first output thereof.

Claim 12

A system according to claim 7, further including a block indicator, responsive to a portion of the contents of said data address and the outputs of said coincidence circuit and said validity data comparator for transferring a prescribed number of bits of said address data in a buffer address register associated with said buffer memory.

Claim 13

A system according to claim 2, wherein said common memory controller comprises means for selecting addresses in said instruction address bus and said operand address bus and transferring said addresses to a memory address register, and a block indicator for converting prescribed bits in the data output of said selecting means into predetermined binary indications for accessing said main memory unit.

Claim 14

A system according to claim 9 wherein said common memory controller further includes a memory data register interconnected with said central processing unit and said main memory unit for temporarily storing data readout of said main memory unit.

Claim 15

A system according to claim 10 wherein said memory controller comprises a control means including service decision circuits respectively associated with each of said first means and second means for determining which of said first means or second means is serviced, a priority decision circuit associated with said service decision circuits and said main memory unit for accessing said main memory unit in response to the outputs of said circuits.