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US3614623A Expired / Lapsed US ⏱️ 0.0 years remaining

Adaptive system for correction of distortion of signals in transmission of digital data

Assignee: Boeing North American Inc
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Filing: 1969-04-21
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Granted: 1971-10-19
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Expires: 1989-04-21
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Abstract

Abstract An adaptive-type system which provides improved arrangements for correction of distortion of digital data sent over a transmission channel. The system includes a data shift register which stores received data bits and cross-correlates these with the signal being received to thereby obtain the impulse response of the transmission channel to provide compensation therefor. Crosscorrelation networks produce a correction signal for compensation by digitally multiplying each of the n most recently received data bits by any residual distortion remaining in a sampling of the received signal after compensation and integrating the respective products. Residual distortion is detected by comparison of the sampling of the received signal after compensation and the signal for the most recent data bit to provide a residual signal. This residual signal is applied to the correlation circuits to produce a final correction signal which eliminates any distortion causing errors in transmission of the digital data. Another embodiment of the invention also compensates for cross-channel distortion arising in a quadrature modulation system.

Inventors

  • 👤 Gerald K Mcauliffe

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 11:08
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03057; H04L25/0307

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 134 words
Digital data apparatus comprising: means for receiving digital data signals; signal correction means coupled to said receiver means for subtracting a correction signal from signals being received to produce corrected received signals; digital storage means coupled to said signal correction means for digital storage of data in said corrected received signals; and residual distortion detection means including correlation means coupled to said digital storage means to provide a correlator output corresponding to the current data being received, said residual distortion detection means being responsive to said correlator output and said corrected received signal to provide a signal indicative of residual distortion in said corrected received signal, said correlator means being responsive to said residual signal and prior digital data stored in said storage means to provide said correction signal for said signal correction means.
Claim 2
Dependent Claim 134 words
Digital data apparatus comprising: means for receiving digital data signals; signal correction means coupled to said receiver means for subtracting a correction signal from signals being received to produce corrected received signals; digital storage means coupled to said signal correction means for digital storage of data in said corrected received signals; and residual distortion detection means including correlation means coupled to said digital storage means to provide a correlator output corresponding to the current data being received, said residual distortion detection means being responsive to said correlator output and said corrected received signal to provide a signal indicative of residual distortion in said corrected received signal, said correlator means being responsive to said residual signal and prior digital data stored in said storage means to provide said correction signal for said signal correction means.
Claim 3
Dependent Claim 143 words
A digital data transmission system comprising: a transmitter for transmitting digital data signals; a receiver for said signals including means for storage of said digital data; a correction circuit means for subtracting s correction signal from said signals being received and for coupling corrected received signals to said storage means; residual distortion detection means coupled to said correction circuit means for detection of any remaining distortion in said corrected received signals to produce a residual distortion signal; and correlation means having inputs coupled to storage means and to said residual detection means for correlating stored digital data and said residual distortion signal to produce a correction signal corrEsponding to the distortion in the signals being received, said correlation means having a correlator output coupled to said correction means for applying said correction signal to said correction circuit means to produce said corrected signals.
Claim 4
Dependent Claim 143 words
A digital data transmission system comprising: a transmitter for transmitting digital data signals; a receiver for said signals including means for storage of said digital data; a correction circuit means for subtracting s correction signal from said signals being received and for coupling corrected received signals to said storage means; residual distortion detection means coupled to said correction circuit means for detection of any remaining distortion in said corrected received signals to produce a residual distortion signal; and correlation means having inputs coupled to storage means and to said residual detection means for correlating stored digital data and said residual distortion signal to produce a correction signal corrEsponding to the distortion in the signals being received, said correlation means having a correlator output coupled to said correction means for applying said correction signal to said correction circuit means to produce said corrected signals.
Claim 5
Dependent Claim 384 words
An adaptive system for correcting for distortion of a signal containing digital data and transmitted via a modulation system wherein a portion of said data is transmitted on a first channel and another portion of said data is transmitted on a second channel, said adaptive system comprising in combination: receiving means for providing a corresponding received signal in each channel; a first storage register having n cells for storing the most recent n data bits received on said fist channel, n being an integer greater than one; comparison means provided for each channel for detecting any distortion remaining in the respective received signals after correction for distortion to produce an output residual signal; means for producing a correction signal comprising; n first correlators, each associated with a corresponding cell of said first storage register, each of said first correlator comprising multiplier means for digitally mutiplying said output with the datum contained in said corresponding cell of said first shift register, and means for integrating the output signal of said multiplier means; a second storage register having m cells for storing the most recently received m data bits received on said second channel, m being an integer greater than one; m second correlators, each associated with a corresponding cell of said second shift register, each of said second correlators comprising; multiplier means for digitally multiplying said output of said first signal sample means with the datum contained in said corresponding cell of said second shift register, and means for integrating the output signal from said multiplier means; m first digital multipliers, each associated with a corresponding one of said first correlators and each comprising means for deriving an output having an amplitude equal to said integrated output signal from said corresponding first correlator and having a sign determined by the datum contained in said corresponding cell of said second storage register; m second digital multipliers, each associated with a corresponding one of said second correlators and each comprising means for deriving an output having an amplitude equal to said integrated output signal for said corresponding second correlator and having a sign determined by the datum contained in said corresponding cell of said second storage register; and means for summing the outputs from each of said first and second digital multipliers to provide said correction signal.
Claim 6
Dependent Claim 384 words
An adaptive system for correcting for distortion of a signal containing digital data and transmitted via a modulation system wherein a portion of said data is transmitted on a first channel and another portion of said data is transmitted on a second channel, said adaptive system comprising in combination: receiving means for providing a corresponding received signal in each channel; a first storage register having n cells for storing the most recent n data bits received on said fist channel, n being an integer greater than one; comparison means provided for each channel for detecting any distortion remaining in the respective received signals after correction for distortion to produce an output residual signal; means for producing a correction signal comprising; n first correlators, each associated with a corresponding cell of said first storage register, each of said first correlator comprising multiplier means for digitally mutiplying said output with the datum contained in said corresponding cell of said first shift register, and means for integrating the output signal of said multiplier means; a second storage register having m cells for storing the most recently received m data bits received on said second channel, m being an integer greater than one; m second correlators, each associated with a corresponding cell of said second shift register, each of said second correlators comprising; multiplier means for digitally multiplying said output of said first signal sample means with the datum contained in said corresponding cell of said second shift register, and means for integrating the output signal from said multiplier means; m first digital multipliers, each associated with a corresponding one of said first correlators and each comprising means for deriving an output having an amplitude equal to said integrated output signal from said corresponding first correlator and having a sign determined by the datum contained in said corresponding cell of said second storage register; m second digital multipliers, each associated with a corresponding one of said second correlators and each comprising means for deriving an output having an amplitude equal to said integrated output signal for said corresponding second correlator and having a sign determined by the datum contained in said corresponding cell of said second storage register; and means for summing the outputs from each of said first and second digital multipliers to provide said correction signal.
Claim 7
Dependent Claim 28 words
The adaptive system defined in claim 3 further comprising means for subtracting said correction signal from said signal received from said first channel to derive a corrected signal.
Claim 8
Dependent Claim 131 words
Means for correcting received digital data signals; subtraction means receiving as one input said received digital data signals; signal correction means for providing a correction signal to said subtraction means for subtraction from said received signals whereby the difference between said received digital data signals and said correction signal is the desired corrected received signal; means for storing the most recently corrected received signal in the form of most recently received data bits, including the current received data bit; means for correlating the most recently stored corrected signal against a residual signal to provide correction signals to said signal correction means; second subtraction means for subtracting the stored current data bit from said corrected received signal to form a residual signal which residual signal is fed to said means for correlating.
Claim 9
Dependent Claim 131 words
Means for correcting received digital data signals; subtraction means receiving as one input said received digital data signals; signal correction means for providing a correction signal to said subtraction means for subtraction from said received signals whereby the difference between said received digital data signals and said correction signal is the desired corrected received signal; means for storing the most recently corrected received signal in the form of most recently received data bits, including the current received data bit; means for correlating the most recently stored corrected signal against a residual signal to provide correction signals to said signal correction means; second subtraction means for subtracting the stored current data bit from said corrected received signal to form a residual signal which residual signal is fed to said means for correlating.
Claim 10
Dependent Claim 90 words
The invention according to claim 5 wherein said means for storing is an n cell register for storing the most recently received n data bits including the current data being received wherein n is an integer greater than two; and wherein said means for correlating is comprised of: n correlators, each associated with a corresponding cell of said storage register, each correlator comprising; multiplier means for digitally multiplying said residual signal with the datum contained in said corresponding cell, and means for integrating the output signal for said multiplier means.
Claim 11
Dependent Claim 43 words
The means for correcting defined in claim 6 wherein n is at least as great as the number of data bits transmitted during the ring out of said impulse response plus an additional correlator for determining the amplitude of the current data bit.
Claim 12
Dependent Claim 65 words
The means for correcting defined in claim 6 wherein said multiplier means comprise means for providing an output signal equal in amplitude to said output at predetermined intervals of each of the bit periods and having a sign corresponding to that of said output if the datum in said corresponding cell is true and opposite to that of said output if said datum is false.
Claim 13
Independent Claim 270 words
A system circuit arrangement for correcting for distortion of digital data sent via a signal channel, said circuit arrangement comprising: a storage register having n cells for storing the most recently received n data bits, including the current data bit, n being an integer greater than one; signal sample means for periodically sampling the signal received from said transmission channel and for providing an output having an amplitude equal to that of said signal at the preceding sample time; n correlators, each associated with a corresponding cell of said storage register, each correlator comprising: multiplier means for digitally multiplying a residual signal with the datum contained in said corresponding cell, and integer means for integrating the output signal from said multiplier means; n digital multipliers, each associated with a corresponding one of said correlators, each of said multipliers comprising means for deriving an output equal in amplitude to said integrated output signal from said corresponding integrator means and having a sign corresponding to that of said integrated signal output if the datum in the cell corresponding to said correlator is true and opposite to that of said integrated signal output if said datum is false; means for summing the output of n- 1 of said digital multipliers to provide a correction signal; means for subtracting said correction signal from said signal received from said channel to derive a corrected received signal; and second subtraction means for subtracting the correlated output current data bit at the output of said correlated n-digital multiplier from the corrected received signal to provide a residual signal which residual signal is fed to said multiplier means.
Claim 14
Independent Claim 270 words
A system circuit arrangement for correcting for distortion of digital data sent via a signal channel, said circuit arrangement comprising: a storage register having n cells for storing the most recently received n data bits, including the current data bit, n being an integer greater than one; signal sample means for periodically sampling the signal received from said transmission channel and for providing an output having an amplitude equal to that of said signal at the preceding sample time; n correlators, each associated with a corresponding cell of said storage register, each correlator comprising: multiplier means for digitally multiplying a residual signal with the datum contained in said corresponding cell, and integer means for integrating the output signal from said multiplier means; n digital multipliers, each associated with a corresponding one of said correlators, each of said multipliers comprising means for deriving an output equal in amplitude to said integrated output signal from said corresponding integrator means and having a sign corresponding to that of said integrated signal output if the datum in the cell corresponding to said correlator is true and opposite to that of said integrated signal output if said datum is false; means for summing the output of n- 1 of said digital multipliers to provide a correction signal; means for subtracting said correction signal from said signal received from said channel to derive a corrected received signal; and second subtraction means for subtracting the correlated output current data bit at the output of said correlated n-digital multiplier from the corrected received signal to provide a residual signal which residual signal is fed to said multiplier means.
Claim 15
Dependent Claim 44 words
The circuit arrangement defined in claim 9 in which said output of the multiplier for the current data bit it compared with the corrected signal to determined the residual distortion in the corrected signal to produce a residual signal for inputs of said correlators.
Claim 16
Dependent Claim 28 words
In conjunction with a multilevel modulation system, the circuit arrangement defined in claim 9 wherein said stored data bits comprise the most significant bits of said digital data.
Claim 17
Dependent Claim 32 words
The circuit arrangement as defined in claim 9 further comprising digital decision means for providing a binary output the sense of which is determined by the sign of said corrected received signal.

References Cited (Backward Citations)

US3404338A Cited
US3366895A Cited
US3524169A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1974-10-18 1975-04-19 1975-10-19 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1978-10-18 1979-04-19 1979-10-19 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1982-10-18 1983-04-19 1983-10-19 $7700.00 Window Closed / Lapsed

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