US3614404A
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US
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Electronic calculator
Assignee: General Electric Co
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Filing: 1969-04-17
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Granted: 1971-10-19
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Expires: 1989-04-17
Abstract
Abstract An inexpensively fabricated electronic calculator for efficiently performing basic mathematical operations including addition, subtraction, multiplication and division is disclosed. In the multiplication operation binary coded numbers are transformed into a unary code using a serial, digit-by-digit technique. A logical design is employed which permits a circuit construction utilizing relatively inexpensive semiconductor devices, specifically of an integrated circuit MOSFET design. In addition and subtraction operations binary-coded decimals are employed throughout, with correction of uncorrected sums being made by suitable modifications of the circuit which permit the adder-subtracter network per se to be traversed twice thereby obviating the need for a separate correction network. A division operation is performed employing multiplication and additionsubtraction circuitry.
Inventors
- 👤 Mark M Garfein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 14:23
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/491; G06F7/4915; G06F7/4917
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
296 words
An electronic calculator for performing multiplication operations of two multidigit binary-coded decimal numbers, comprising: a. a first storage network for storing one of said numbers, said first storage network including four multistage registers, one register for each binary bit order of the stored decimal digits, b. a second storage network for storing the other of said numbers, said second storage network including four multistage registers, one register for each binary bit order of of the stored decimal digits, c. A four-stage binary-coded decimal counter, d. a first switch network for applying in parallel the binary bits of each digit of said one number to the stages of said binary-coded decimal counter, e. a binary-coded decimal rate multiplier for generating during a given period unary pulses proportional in number to an applied input quantity, f. a second switch network for applying in parallel the binary bits of each digit of said other number to said rate multiplier for determining the number of unary pulses generated during each given period, g. an accumulator network comprising multiple binary-coded decimal counter stages, one for each bit order of the processed decimal digits, h. a third switch network for applying the generated unary pulses from said rate multiplier in an advancing succession to the counter stages of said accumulator network, i. means for applying a trigger signal to said binary-coded decimal counter once each given period for causing said binarycoded decimal counter to count one unit, and j. detection means responsive to the count in said decimal counter for terminating the generation of said unary pulses from said rate multiplier upon said count reaching a given reference value, whereby the generated unary pulses are a function of the product of digits applied to said decimal counter and to said rate multiplier.
Claim 2
Dependent Claim
296 words
An electronic calculator for performing multiplication operations of two multidigit binary-coded decimal numbers, comprising: a. a first storage network for storing one of said numbers, said first storage network including four multistage registers, one register for each binary bit order of the stored decimal digits, b. a second storage network for storing the other of said numbers, said second storage network including four multistage registers, one register for each binary bit order of of the stored decimal digits, c. A four-stage binary-coded decimal counter, d. a first switch network for applying in parallel the binary bits of each digit of said one number to the stages of said binary-coded decimal counter, e. a binary-coded decimal rate multiplier for generating during a given period unary pulses proportional in number to an applied input quantity, f. a second switch network for applying in parallel the binary bits of each digit of said other number to said rate multiplier for determining the number of unary pulses generated during each given period, g. an accumulator network comprising multiple binary-coded decimal counter stages, one for each bit order of the processed decimal digits, h. a third switch network for applying the generated unary pulses from said rate multiplier in an advancing succession to the counter stages of said accumulator network, i. means for applying a trigger signal to said binary-coded decimal counter once each given period for causing said binarycoded decimal counter to count one unit, and j. detection means responsive to the count in said decimal counter for terminating the generation of said unary pulses from said rate multiplier upon said count reaching a given reference value, whereby the generated unary pulses are a function of the product of digits applied to said decimal counter and to said rate multiplier.
Claim 3
Dependent Claim
56 words
An electronic calculator as in claim 1 wherein said first switch network is operated in a first digital sequence and said second switch network is operated in a second digital sequence having a multiple relationship with said first digital sequence so as to provide a cross products of The digits of said two binary-coded decimal numbers.
Claim 4
Dependent Claim
43 words
An electronic calculator as in claim 2 wherein said binary-coded decimal counter is operated in a countdown mode and said detection means comprises a zero detector responsive to a zero count of said decimal counter for terminating the generation of said unary pulses.
Claim 5
Dependent Claim
16 words
An electronic calculator as in claim 3 which employs integrated circuit MOSFET devices in its construction.
Claim 6
Dependent Claim
254 words
An electronic calculator for performing division operations of two decimal numbers, comprising: first storage means for storing the dividend and divisor, b. comparator means for comparing the most significant digit of the divisor stored in said first storage means with a first constant and generating a first output when said constant is the larger value, a second output when said constant is the lesser value or an equal value, c. first multiplier means responsive to said first output of said comparator means for multiplying said dividend and divisor by a second constant to provide a modified dividend and divisor, d. means for coupling said modified dividend and divisor back to said first storage means, e. second storage means for storing a given value and having a third constant initially stored therein, f. second multiplier means responsive to said second comparator for multiplying said modified divisor by the value stored in said second storage means, g. subtracter means for subtracting the output of said second multiplying means from said second constant, h. third multiplier means for multiplying the output of said subtracter means by the value stored in said second storage means, the output of said third multiplier means being coupled to said second storage means for updating the stored value, after several updatings said stored value closely approximating the reciprocal quantity of the modified divisor, and i. fourth multiplier means for multiplying the updated value stored in said second storage means by said modified dividend for obtaining the quotient of said two decimal numbers.
Claim 7
Dependent Claim
254 words
An electronic calculator for performing division operations of two decimal numbers, comprising: first storage means for storing the dividend and divisor, b. comparator means for comparing the most significant digit of the divisor stored in said first storage means with a first constant and generating a first output when said constant is the larger value, a second output when said constant is the lesser value or an equal value, c. first multiplier means responsive to said first output of said comparator means for multiplying said dividend and divisor by a second constant to provide a modified dividend and divisor, d. means for coupling said modified dividend and divisor back to said first storage means, e. second storage means for storing a given value and having a third constant initially stored therein, f. second multiplier means responsive to said second comparator for multiplying said modified divisor by the value stored in said second storage means, g. subtracter means for subtracting the output of said second multiplying means from said second constant, h. third multiplier means for multiplying the output of said subtracter means by the value stored in said second storage means, the output of said third multiplier means being coupled to said second storage means for updating the stored value, after several updatings said stored value closely approximating the reciprocal quantity of the modified divisor, and i. fourth multiplier means for multiplying the updated value stored in said second storage means by said modified dividend for obtaining the quotient of said two decimal numbers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-18 | 1975-04-19 | 1975-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-18 | 1979-04-19 | 1979-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-18 | 1983-04-19 | 1983-10-19 | $7700.00 | Window Closed / Lapsed |