US3610908A
Expired / Lapsed
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Electronic integrator system
Assignee: Cutler Hammer Inc
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Filing: 1970-02-09
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Granted: 1971-10-05
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Expires: 1990-02-09
Abstract
Abstract A solid-state integrator that receives tow information signals, namely, a weight signal and a speed signal, integrates these signals and provides an output signal proportional to the product thereof that is indicative of total weight of material that has passed a scale. The weight signal comes from the scale and is a negative DC voltage having an amplitude proportional to the weight per unit length of conveyor belt. The speed signal comes from a belt rider measuring wheel operated pulse generator and consists of 100 uniform width pulses per foot of belt travel. An amplifier at the integrator input amplifies the weight signal and has an input bias adjusting potentiometer for zero calibration and an attenuation adjusting potentiometer at its output for span calibration. Span refers to the correct total weight of a run of several belt circuits with a test weight. Zero refers to zero total weight of a run of several belt circuits empty. For integration purposes, the speed pulses are shaped, get in step with the clock, and are stretched to desired width by a clock controlled preset pulse width generator. This pulse, called ''''fill'''' pulse, whose width is precisely controlled by the clock, operates an analog gate via a gate driver, allowing DC voltage representing weight on a scale to enter the integrator and charge the integrating capacitor therein. The integrator is bidirectional and will accumulate both positive and negative charges and will provide a DC voltage having a polarity and amplitude proportional to the algebraic sum thereof. The integrator receives two control signals, namely, a fill pulse described previously and ''''dipout'''' pulses, the latter being essential in an integration process -- without them the integrator would saturate. Dipout pulses can be in step with the clock pulse, or in step with the inverted clock pulse, depending on demand. The dipout pulses operate the other analog gate via a gate driver which allows the positive or negative half-cycles of the sine wave voltage to discharge the integrator capacitor. Dipout is started by a voltage level detector so that the integrator does not exceed its capacity in continuous running. The uniform dipout quantities are counted in a forward-backward operable weight totalizer to provide a running indication of the total weight of material that has passed over the scale and for other control and indication purposes. This method of integration -- where the sine wave drives the transducer, generates clock and inverted clock pulses, controls the pulse width of the fill pulse and the pulse width of the dipout pulse, and the same sine wave is used for dipping out the integrator -- all this provides ''''bridging action,'''' that is, automatic self-compensation in response to frequency or amplitude variation in the sine wave voltage so that no error will be introduced in the output.
Inventors
- 👤 Raymond Karosas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 07:58
CPC Classifications
G; G01; G01G; G01G11/00; G01G11/14; G01G11/16; G01G11/18; G06; G06G; G06G7/00; G06G7/12; G06G7/18; G06G7/184; G06G7/186; H; H03; H03M; H03M1/00; H03M1/12; H03M1/22; H03M1/24; H03M1/28; H03M1/30
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
252 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition; means for providing an intermittent electrical signal comprising a train of uniform length fill pulses that varies in frequency as a function of a second external condition; first gating means operably be said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; a source of sine wave voltage; a clock pulse circuit controlled by said sine wave voltage for providing a train of clock pulses synchronized with the cycles of said sine wave; digital means controlled by said control signal and said clock pulses and being operable by each clock pulse during receipt of said control signal for forming a dipout control pulse for gating a half-cycle of said sine wave as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information pulses under the control of said clock pulse thereby changing the integrated voltage back by a uniform decremental amount; and means operable by said digital means upon formation of said dipout pulse for providing a count pulse that is adapted to be applied to a totalizer.
Claim 2
Dependent Claim
252 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition; means for providing an intermittent electrical signal comprising a train of uniform length fill pulses that varies in frequency as a function of a second external condition; first gating means operably be said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; a source of sine wave voltage; a clock pulse circuit controlled by said sine wave voltage for providing a train of clock pulses synchronized with the cycles of said sine wave; digital means controlled by said control signal and said clock pulses and being operable by each clock pulse during receipt of said control signal for forming a dipout control pulse for gating a half-cycle of said sine wave as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information pulses under the control of said clock pulse thereby changing the integrated voltage back by a uniform decremental amount; and means operable by said digital means upon formation of said dipout pulse for providing a count pulse that is adapted to be applied to a totalizer.
Claim 3
Dependent Claim
109 words
The invention defined in claim 1, wherein said means for providing an analog electrical signal comprises: a transducer powered by said sine wave voltage and adapted to be controlled by the first external condition thereby to provide said analog electrical signal; and the use of the same sine wave voltage for both said transducer and said dipout voltage provides effective compensation in the event of sine wave amplitude variation in that any increase in the sine wave amplitude will increase the information voltage going into the integrator circuit but will also proportionally increase the dipout voltage and vice versa to prevent introduction of any error in the integrator output.
Claim 4
Dependent Claim
168 words
The invention defined in claim 1, wherein said means for providing an intermittent electrical signal comprising a train of uniform length fill pulses that vary in frequency as a function of a second external condition comprises: means for providing a condition indicative pulse signal having a frequency proportional to said second external condition; means controlled by said clock pulses to provide for each said condition indicative pulse a uniform length fill pulse having a length equal to a predetermined number of clock pulses; and the use of the sine wave voltage for both said dipout voltage and said clock pulses that determine the length of the gating period for said analog electrical signal provides effective compensation in the event of the sine wave frequency decrease in that any decrease in such frequency will proportionally increase the fill pulse width and the information voltage area but will also proportionally increase the area under the dipout half-cycle and vice versa to prevent introduction of any error in the integrator output.
Claim 5
Dependent Claim
90 words
The invention defined in claim 1, wherein said means for providing an analog electrical signal comprises: an amplifier; a transducer adapted to be controlled by the first external condition to provide a voltage to the input of said amplifier; means for applying an adjustable bias voltage to the input of said amplifier for zero calibration of the integrator system; and adjustable attenuator means coupling the output of said amplifier to said first gating means for correct totalizing calibration of the integrating system and being noninteracting with said zero calibration means.
Claim 6
Dependent Claim
58 words
The invention defined in claim 1, wherein said means operable by said digital means upon formation of said dipout control pulse for providing a count pulse that is adapted to be applied to a totalizer comprises: third gating means effective when activated for passing said count pulse; and means for activating said third gating means under predetermined conditions.
Claim 7
Dependent Claim
63 words
The invention defined in claim 5, wherein said means for activating said third gating means under predetermined conditions comprises: pulse delay generator means operated by each fill pulse for activating said third gating means for the duration of said fill pulse and for a predetermined additional time interval whereafter said third gating means blocks the passage of any spurious pulses that might occur.
Claim 8
Dependent Claim
46 words
The invention defined in claim 5, wherein said means for activating said third gating means under predetermined conditions comprises: an interlock timer operable to activate said third gating means when the integrator is operating and for a predetermined time interval after the system is turned off.
Claim 9
Dependent Claim
71 words
The invention defined in claim 1, wherein said integrator circuit comprises: a field-effect transistor circuit connected in the source follower mode to provide desired isolation for the integrator so that no voltage is lost or gained by the integrator when said level detector means operate and including means for applying the integrated voltage at its gate and for applying from its source terminal an output voltage to said level detector means.
Claim 10
Dependent Claim
37 words
The invention defined in claim 1, wherein said integrator circuit comprises: means for integrating information voltages of either or both polarities and for providing either a positive output voltage or a negative output voltage in accordance therewith.
Claim 11
Dependent Claim
55 words
The invention defined in claim 9, wherein said level detector means comprises: a positive level detector responsive to said integrated output voltage exceeding a predetermined positive value for providing said control signal; and a negative level detector responsive to said integrated output voltage falling below a predetermined negative value for providing another like control signal.
Claim 12
Dependent Claim
122 words
The invention defined in claim 10, wherein said digital means comprises: means for inverting said clock pulses to provide both clock pulses and inverted clock pulses, the clock pulses being in synchronism with the positive half-cycles of said sine wave voltage and the inverted clock pulses being in synchronism with the negative half-cycles of said sine wave voltage; first logic means operated by the first control signal and the inverted clock pulses for providing dipout control pulses for gating the positive half-cycles of the sine wave voltage as dipout voltages; and second logic means operated by the other control signal and the clock pulses for providing dipout control pulses for gating the negative half-cycles of the sine wave voltage as dipout voltages.
Claim 13
Dependent Claim
283 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition; means for providing an intermittent electrical signal comprising a train of uniform length fill pulses that vary in frequency as a function of a second electrical condition; first gating means operable by said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; a source of sine wave voltage; a clock pulse generator circuit controlled by said sine wave voltage for providing a train of clock pulses and inverted clock pulses synchronized with the positive and negative half-cycles of said sine wave voltage; digital means controlled by said control signal and said clock and inverted clock pulses and being operable by a clock or inverted clock pulse during receipt of said control signal for forming a dipout pulse; second gating means responsive to said dipout pulse for gating a half-cycle of said sine wave voltage as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information voltage under the control of said dipout pulse thereby reducing or increasing the integrated voltage by a uniform amount; and means operable by said digital means upon formation of said dipout pulses in step with clock pulses or inverted clock pulses for providing count pulses that are adaptable to applied to an add-subtract counter.
Claim 14
Dependent Claim
283 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition; means for providing an intermittent electrical signal comprising a train of uniform length fill pulses that vary in frequency as a function of a second electrical condition; first gating means operable by said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; a source of sine wave voltage; a clock pulse generator circuit controlled by said sine wave voltage for providing a train of clock pulses and inverted clock pulses synchronized with the positive and negative half-cycles of said sine wave voltage; digital means controlled by said control signal and said clock and inverted clock pulses and being operable by a clock or inverted clock pulse during receipt of said control signal for forming a dipout pulse; second gating means responsive to said dipout pulse for gating a half-cycle of said sine wave voltage as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information voltage under the control of said dipout pulse thereby reducing or increasing the integrated voltage by a uniform amount; and means operable by said digital means upon formation of said dipout pulses in step with clock pulses or inverted clock pulses for providing count pulses that are adaptable to applied to an add-subtract counter.
Claim 15
Dependent Claim
68 words
The invention defined in claim 12, wherein said means operable by said digital means upon formation of said dipout pulse in step with clock pulses or inverted clock pulses for providing count pulses that are adaptable to be applied to an add-subtract totalizer comprises: third gating means effective when activated for passing add or subtract pulses; and means for activating said third gating means under a predetermined condition.
Claim 16
Dependent Claim
282 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition such as weight; means for providing an intermittent electrical signal comprising a train of rate pulses that varies in frequency as a function of a second external condition such as speed; a source of AC voltage; a clock pulse circuit controlled by said AC voltage for providing a train of clock pulses in step with the cycles of said AC voltage; means controlled jointly by said rate pulses and said clock pulses for providing a train of uniform length fill pulses having a frequency proportional to the second external condition; first gating means operable by said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; static switching means operable by a clock pulse when said control signal is present for forming a dipout control pulse; second gating means responsive to said dipout control pulse for gating a half-cycle of said AC voltage as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information voltage under the control of said dipout pulse thereby changing the integrated voltage back by a uniform amount; and means operable by said static switching means when it forms said dipout control pulse for providing a count signal that is adapted to operate a totalizer.
Claim 17
Dependent Claim
282 words
In an electronic integrator system, the combination comprising: means for providing an analog electrical signal that varies in amplitude as a function of a first external condition such as weight; means for providing an intermittent electrical signal comprising a train of rate pulses that varies in frequency as a function of a second external condition such as speed; a source of AC voltage; a clock pulse circuit controlled by said AC voltage for providing a train of clock pulses in step with the cycles of said AC voltage; means controlled jointly by said rate pulses and said clock pulses for providing a train of uniform length fill pulses having a frequency proportional to the second external condition; first gating means operable by said fill pulses for gating said analog signal to provide a train of uniform length variable amplitude information voltages; an integrator circuit for receiving said information voltages to provide an output voltage proportional in amplitude to the integral thereof; level detector means responsive to said integrated output voltage when it exceeds a predetermined value for providing a control signal; static switching means operable by a clock pulse when said control signal is present for forming a dipout control pulse; second gating means responsive to said dipout control pulse for gating a half-cycle of said AC voltage as a dipout voltage, said gated half-cycle being of the proper polarity relative to the polarity of said information voltage under the control of said dipout pulse thereby changing the integrated voltage back by a uniform amount; and means operable by said static switching means when it forms said dipout control pulse for providing a count signal that is adapted to operate a totalizer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-10-04 | 1975-04-05 | 1975-10-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-10-04 | 1979-04-05 | 1979-10-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-10-04 | 1983-04-05 | 1983-10-05 | $7700.00 | Window Closed / Lapsed |