Digital transmission system employing identifiable marker streams on pulses to fill all idle channels

Claim 2

A pulse transmission system comprising, in combination, a plurality of N-sources of pulse information distributed along a digital transmission line connected between a first such source and a receiver, means at the first source to establish a frame of N-time-slots on said transmission line, means at said first source to insert pulse signals from said first source into a first time slot, means at said first source to insert predetermined pulse signals into all time slots except said first time slot, means at each succeeding pulse source between said first source and said receiver to ascertain the occurrence of an information signal and one of said predetermined signals in adjacent time slots and to delete said predetermined signal and insert a pulse information signal in that time slot.

Claim 3

Apparatus in accordance with claim 1 wherein said means at said first source to establish a frame of N-time-slots on said transmission line comprises a divide by N-circuit connected to receive clock signals from a local clock source having a pulse repetition rate equal to that of said transmission line and generate pulses in three consecutive time slots during each group of N time slots.

Claim 4

Apparatus in accordance with claim 2 wherein said means at said first source to insert predetermined pulse signals into all time slots except said first time slot comprises, a divide by four circuit connected to receive the signals applied to said divide by N-circuit, a pair of AND gates, means to apply the output of said divide by four circuit to one of said AND gates, means to invert the output of said divide by four circuit and apply the resulting inverted output signal to the second of said AND gates, a divide by three circuit, means to apply pulses at the frame rate to the input of said divide by three circuit, means to generate signals within said divide by three circuit that are ''''1s'''' for two frames and ''''0'''' for the next succeeding frame and apply said signal to one of said AND gates, means to generate in said divide by three circuit a signal that is ''''0'''' for two frames and a ''''1'''' for the next succeeding frame and apply said signal to a second of said AND gates, and means to enable said two AND gates in all time slots except that which occurs when said second pulse of said group of three pulses is being generated by said divide by N-circuit.

Claim 5

Apparatus in accordance with claim 3 in which said means at each succeeding pulse source between said first source and said receiver to ascertain the occurrence of an information signal and one of said predetermined signals in adjacent time slots comprises, in combination, first apparatus to ascertain the presence of said predetermined signal in said time slot in which said second pulse of said group of three pulses is generated bY said divide by three circuit, second apparatus to determine the existence of a predetermined relationship between the signals present in the first time slot of said group of three time slots in which pulses are generated by said divider circuit, and means to inhibit clock pulses from being applied to said divider which establishes said frame in the event said apparatus does not determine the presence of said signal, and means to inhibit clock pulses from being applied to said divider in the event said second apparatus fails to determined the existence of said predetermined relationship.