Addressable list memory systems

Claim 2

A memory system which is accessible for the operations of reading or writing words comprising at least one main list memory means of the pushdown type for storing a plurality of words and at least one auxiliary list memory means of the pushdown type for storing a plurality of words, only said main list memory means storing words at the start of a reading or writing operation, address register means for storing the address of a desired word, first transfer means for sequentially transferring words from said main list memory means to said auxiliary list memory means, available address indicating means for indicating the address of each word as it is being so transferred, comparator means for comparing the address of a desired word stored in said address register means and the address being indicated by said available address indicating means for signaling when a particular relationship exists between the addresses being compared, means responsive to the signaling

Claim 3

The memory system of claIm 1 wherein the stored words include key portions and said available address indicating means includes means for indicating the available address in accordance with a key portion of each of the words being sequentially transferred.

Claim 4

The memory system of claim 2 wherein said comparator means includes means for indicating an equality between said key portions and the address stored in said address register means.

Claim 5

The memory system of claim 1 wherein said main list memory means includes a plurality of word register levels, said address register means stores a level number, said available address indicating means includes a counter means which is unit incremented each time a word is transferred from said main list memory means to said auxiliary list memory means for indicating the number of the then available level, and said comparator means senses for a given relationship between the level numbers indicated by said counter means.

Claim 6

A memory system which is accessible for the operations of reading or writing words comprising at least one mean list memory means of the pushdown type including 2n register levels for storing words, where n is an integer, at least one auxiliary list memory means of the pushdown type including 2n register levels for storing words, address register means for storing a number representing a desired level between 1 and 2n, controllable transfer means for sequentially transferring words in a first direction from said main list memory means to said auxiliary list memory means or in a second direction from said auxiliary list memory means to said main memory means, counter means counting at least the number of transfers between said list memory means during a reading or writing operation for storing a number representing the available level of at least one of said list memory means, comparator means for comparing the number stored in said address register means and the number stored in said counter means and for signalling when a particular relationship exists between said numbers being compared, access control means responsive to the signaling of said comparator means for causing the reading of a word from or the writing of a word into the then available level of one of said list memory means, and direction control means for controlling said controllable transfer means to transfer words in one of said directions.

Claim 7

A memory system which is accessible for the operations of reading or writing words comprising at least one mean list memory means of the pushdown type including 2n register levels for storing words, where n is an integer, at least one auxiliary list memory means of the pushdown type including 2n register levels for storing words, address register means for storing a number representing a desired level between 1 and 2n, controllable transfer means for sequentially transferring words in a first direction from said main list memory means to said auxiliary list memory means or in a second direction from said auxiliary list memory means to said main memory means, counter means counting at least the number of transfers between said list memory means during a reading or writing operation for storing a number representing the available level of at least one of said list memory means, comparator means for comparing the number stored in said address register means and the number stored in said counter means and for signalling when a particular relationship exists between said numbers being compared, access control means responsive to the signaling of said comparator means for causing the reading of a word from or the writing of a word into the then available level of one of said list memory means, and direction control means for controlling said controllable transfer means to transfer words in one of said directions.

Claim 8

The memory system of claim 5 wherein said counter means includes means for indicating when at least n transfers in one of said directions occur between said list memory means before the desired level is accessed, and said control means including means responsive at least to said indicating means of said counter means for controlling said controllable transfer means to continue transfers in said one direction until the words of all 2n levels of the source list memory means are stored in the receiving list memory means associated with said one direction of transfer or to cause transfer in the other of said directions until the words of all 2n levels are stored in said source list memory means after said desired level is accessed in accordance with whether or not said indicating means of said counter means indicates that at least n transfers in said one of said directions had occurred before said desired level was accessed.

Claim 9

The memory system of claim 6 further including means for indicating when the words of all 2n levels are transferred to one of said list memory means.

Claim 10

The memory system of claim 6 further including means for remembering which of said list memory means is storing the words.

Claim 11

The memory system of claim 6 wherein said counter means is presettable to different count values and is controllable to incrementally or decrementally count, said comparator means includes means for indicating the equality of the two numbers being compared and also which of the numbers is the greater, further control means for rendering said accesS control means operative when said comparator means indicates an equality of the numbers being compared, and said direction control means responsive to said comparator means for controlling said controllable transfer means to transfer words in a direction determined by which of the two numbers being compared is the greater, and further comprising means responsive to the signaling of said comparator means to cause said counter means to unit increment or unit decrement during the transfer of words between said list memory means as determined by which of the two numbers being compared is the greater and means for presetting said counter means at the start of each read or write operation.

Claim 12

The memory system of claim 9 further including means for transmitting to said presetting means a number related to the count stored in said counter means when said comparator means indicates an equality of the numbers being compared.

Claim 13

A memory system which is accessible for the operations of reading or writing words comprising at least one first-in, first-out list memory means of the queue type for storing a plurality of words, said list memory means having a word input and a word output, address register means for storing the address of a desired word, transfer means for sequentially transferring words from said word output of said list memory means to said word input of said list memory means, available address indicating means for indicating the address of each word as it being so transferred, comparator means for comparing the address of the desired word stored in said address register means and the address being indicated by said available address indicating means for signaling when a particular relationship exists between the addresses being compared, and means responsive to the signaling of said comparator means for causing the reading of a word from or the writing or a word into one of said list memory means.

Claim 14

A memory system which is accessible for the operations of reading or writing words comprising at least one first-in, first-out list memory means of the queue type for storing a plurality of words, said list memory means having a word input and a word output, address register means for storing the address of a desired word, transfer means for sequentially transferring words from said word output of said list memory means to said word input of said list memory means, available address indicating means for indicating the address of each word as it being so transferred, comparator means for comparing the address of the desired word stored in said address register means and the address being indicated by said available address indicating means for signaling when a particular relationship exists between the addresses being compared, and means responsive to the signaling of said comparator means for causing the reading of a word from or the writing or a word into one of said list memory means.

Claim 15

The memory system of claim 11 wherein the stored words including key portions and said available address indicating means includes means for indicating the available address in accordance with a key portion of each of the words being sequentially transferred.

Claim 16

The memory system of claim 11 wherein said main list memory means includes a plurality of word register levels, said address register means stores a level number, said available address indicating means includes a counter means which is unit incremented each time a word is transferred from said word output of said list memory means for indicating the number of the then available level, and said comparator means senses for a given relationship between the level number stored in said address register means and the level numbers indicated by said counter means.

Claim 17

The memory system of claim 13 wherein said levels have an initial order, and further comprising means for restoring said levels to said initial order after said comparator senses said given relationship.

Claim 18

The memory system of claim 13 further comprising means storing the count of said counter means after said comparator means senses said given relationship for subsequent presetting said counter means to said count at the start of another operation of reading or writing.

Claim 19

A memory system comprising at least one main list memory means having a plurality of interconnected registers for storing a plurality of words and at least one auxiliary list memory means having a plurality of interconnected registers for storing a plurality of words, means for indicating a desired word address, means for sequentially transferring words between said main list memory means and said auxiliary list memory means, means for indicating an address for each word being transferred between said memory means, means for indicating when a predetermined relationship exists between the desired word address and the address of the word being transferred, register means, and means responsive to said relationship indicating means for effecting a transfer Of a word between said register means and one of said list memory means.

Claim 20

A memory system comprising at least one main list memory means having a plurality of interconnected registers for storing a plurality of words and at least one auxiliary list memory means having a plurality of interconnected registers for storing a plurality of words, means for indicating a desired word address, means for sequentially transferring words between said main list memory means and said auxiliary list memory means, means for indicating an address for each word being transferred between said memory means, means for indicating when a predetermined relationship exists between the desired word address and the address of the word being transferred, register means, and means responsive to said relationship indicating means for effecting a transfer Of a word between said register means and one of said list memory means.

Claim 21

The memory system of claim 16 wherein said means responsive to said relationship indicating means includes means for reading a word from one of said list memory means and transferring said word to said register means.

Claim 22

The memory system of claim 16 wherein said register means includes a source of words and said means responsive to said relationship indicating means includes means for receiving a word from said source of words and for recording said word into one of said list memory means.

Claim 23

The memory system of claim 16 further comprising another main list memory means and means for selecting one of said main list memory means to cooperate with said one auxiliary list memory means during the sequential word transfers.

Claim 24

The memory system of claim 16 wherein at least one of said list memory means is a last-in, first-out pushdown type list memory.

Claim 25

The memory system of claim 16 wherein each of said list memory means is a last-in, first-out pushdown list memory.