Method and apparatus for deallocating small memory spaces assigned to a computer program

Claim 3

The method of claim 1 further including the steps of: sensing all of the status bits in the located status word, signaling when all of the status bits in the status word are indicating an Available status for the associated memory areas, and storing the base address identified in the area status word.

Claim 4

The method of claim 2 further including the steps of: removing the area status word from the list in memory when all the status bits are sensed and signaled as being in the Available status.

Claim 5

The method of claim 1 further including the steps of: sensing when the last status word has been read out of the list in memory, and signaling an Interrupt condition after the last status word has been sensed.

Claim 6

In a digital computer system, apparatus for deallocating memory space comprising: An addressable memory having a plurality of memory status words stored therein, each status word having a first group of bits defining the base address of a block of sequential address positions in the memory, a second group of bits defining a particular size of memory space for the associated block, and a third group of bits defining the availability status of each memory space within the associated block; means for reading out the status words from the memory in predetermined sequence; a first register for storing the address of the memory to be deallocated; means for comparing the first group of bits of each status with address in the first register, the comparing means signalling when the first group of bits is equal to or less than the address in the first register, means responsive to the comparing means when signalling that the first group of bits is less than the address for incrementing the first group of bits by the second group of bits of the same status word, said last-named means including means responsive to the number of status bits in the third group of bits for repeating said incrementing of the first group of bits by the second group of bits a number of times corresponding to the number of bits in said third group of bits of the status words, the incremented group of bits being applied to the comparing means; means for interrupting said incrementing means when the comparing means signals that the incremented group of bits equals the address in the first register, and means responsive to comparing means signalling an equal condition for selectively resetting the corresponding status bit in the third group of bits of the status word to indicate the addressed area in the block is again available.

Claim 7

In a digital computer system, apparatus for deallocating memory space comprising: An addressable memory having a plurality of memory status words stored therein, each status word having a first group of bits defining the base address of a block of sequential address positions in the memory, a second group of bits defining a particular size of memory space for the associated block, and a third group of bits defining the availability status of each memory space within the associated block; means for reading out the status words from the memory in predetermined sequence; a first register for storing the address of the memory to be deallocated; means for comparing the first group of bits of each status with address in the first register, the comparing means signalling when the first group of bits is equal to or less than the address in the first register, means responsive to the comparing means when signalling that the first group of bits is less than the address for incrementing the first group of bits by the second group of bits of the same status word, said last-named means including means responsive to the number of status bits in the third group of bits for repeating said incrementing of the first group of bits by the second group of bits a number of times corresponding to the number of bits in said third group of bits of the status words, the incremented group of bits being applied to the comparing means; means for interrupting said incrementing means when the comparing means signals that the incremented group of bits equals the address in the first register, and means responsive to comparing means signalling an equal condition for selectively resetting the corresponding status bit in the third group of bits of the status word to indicate the addressed area in the block is again available.

Claim 8

Apparatus as defined in claim 5 further including: a second register for storing in coded form the size of the memory space to be deallocated, means for comparing the second group of bits in each status word read out of memory, said last-named comparing means signalling when the second group of bits in the status word is equal to the size in the second register, and means responsive to said last-named comparing means when it signals an equal condition for activating said means for comparing the first group of bits with the address in the first register.

Claim 9

Apparatus as defined in claim 5 further including means responsive to the resetting of the status bit for sensing if all the status bits in the associated status word have been reset to an Available status, and means responsive to said sensing means when all the status bits have been reset to an Available status for removing the associated status word from the list in memory.

Claim 10

An internally programmed computer comprising: an addressable memory, the memory having a group of memory area status words stored in a predetermined address sequence in the memory, each status word including a first group of bits specifying the base address of a block of words in memory, a second group of bits specifying the size of a memory area, and a third group of bits identifying the availability status of each area in the block, means for reading out each of said status words in sequence from the memory, first register means storing in coded form a number identifying the size of a memory area to be deallocated, means for comparing the second group of bits of each status word as it is read out of memory with the number in said first register means to locate a status word in which the second group of bits specifies the same area size as the number in the first register, a second register for storing in coded form an address of a space in memory to be changed in status, means responsive to the comparing means when a status word is located in which the second group of bits is equal to the number in the first register for applying the first group of bits of the same status word and the address in the second register to comparing means, means responsive to an output indication of the comparing means that the address in the second register is larger in value than the first group of bits for repeatedly incrementing the first group of bits by the second group of bits of the same status word, means for counting the number of times the first group of bits of the status word is incremented, means for interrupting the incrementing means when the comparing means indicates the incremented first group of bits is equal in value to the address in the second register; means synchronized with said incrementing means for sensing each of the status bits in the third group of bits in the status word in sequence with incrementing the first group of bits; means responsive to the comparing means for changing the particular status bit sensed by the sensing means when the comparing means indicates the incremented first group of bits is equal in value to the address, and means responsive to the counting means for interrupting the incrementing means and reading out the next status word in memory when the counting means reachEs a predetermined count condition.

Claim 11

An internally programmed computer comprising: an addressable memory, the memory having a group of memory area status words stored in a predetermined address sequence in the memory, each status word including a first group of bits specifying the base address of a block of words in memory, a second group of bits specifying the size of a memory area, and a third group of bits identifying the availability status of each area in the block, means for reading out each of said status words in sequence from the memory, first register means storing in coded form a number identifying the size of a memory area to be deallocated, means for comparing the second group of bits of each status word as it is read out of memory with the number in said first register means to locate a status word in which the second group of bits specifies the same area size as the number in the first register, a second register for storing in coded form an address of a space in memory to be changed in status, means responsive to the comparing means when a status word is located in which the second group of bits is equal to the number in the first register for applying the first group of bits of the same status word and the address in the second register to comparing means, means responsive to an output indication of the comparing means that the address in the second register is larger in value than the first group of bits for repeatedly incrementing the first group of bits by the second group of bits of the same status word, means for counting the number of times the first group of bits of the status word is incremented, means for interrupting the incrementing means when the comparing means indicates the incremented first group of bits is equal in value to the address in the second register; means synchronized with said incrementing means for sensing each of the status bits in the third group of bits in the status word in sequence with incrementing the first group of bits; means responsive to the comparing means for changing the particular status bit sensed by the sensing means when the comparing means indicates the incremented first group of bits is equal in value to the address, and means responsive to the counting means for interrupting the incrementing means and reading out the next status word in memory when the counting means reachEs a predetermined count condition.

Claim 12

Apparatus as defined in claim 8 further including means responsive to said status bit changing means for indicating when the status bit is changed to the same status as all the other status bits in third group of bits of the status word, and means responsive to said indicating means for erasing the status word from the list of status words in memory.

Claim 13

Apparatus as defined in claim 9 further including means responsive to said indicating means for reading out the same status word from memory and transferring the base address identified by the first group of bits of the status word to the second register.