US3593313A
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Calculator apparatus
Assignee: Monroe Systems for Business Inc
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Filing: 1969-12-15
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Granted: 1971-07-13
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Expires: 1989-12-15
Abstract
Abstract An electronic calculator apparatus capable of storing a plurality of multidigit numbers and of performing operations with respect to those numbers. Operations are defined by two levels of instructions; i.e.; (1) a user level specified by keyboard actuations, and (2) an internal or microprogrammed level comprised of instructions primarily extracted from a program read-only memory. In operation, user or keyboard instructions initiate subroutines which are read from the program read-only memory and which may be comprised of a sequence of up to several thousand internal instructions. The calculator apparatus includes an alterable data memory comprised of a plurality of shift registers. Input and output control logic respectively control the flow of data to and from the data memory. The control logic is responsive to control information, read from a control readonly memory, specified by data modifying internal instructions delivered to an instruction register from the program read-only memory. Instruction codes can also be delivered to the instruction register from compiler logic responsive to keyboard actuations. The instruction sequence read from the program memory is defined by a program counter which is normally successively incremented by one. However, certain instructions can cause the program counter to skip, jump, or branch. When the program counter is caused to branch, the prior program count plus one is stored in a ''''last-in first-out'''' memory for later recall. The compiler logic functions to convert keyboard actuations presenting a problem in algebraic notation to a ''''Polish'''' notation required for calculator operation. A learn mode programmer can optionally be included for storing programs comprised of keyboard level or internal level instructions. The learn mode programmer can be loaded either from the keyboard or from some storage medium such as punched cards. Once the programmer has been loaded it is treated by the calculator just as if it constituted a portion of the program read-only memory.
Inventors
- 👤 Carlos A Tomaszewski
- 👤 Timothy A R Goodliffe
- 👤 Norman J Grannis
- 👤 Irving Sperling
- 👤 Connable F Wills
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:06
CPC Classifications
G; G06; G06F; G06F15/00
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
250 words
An electronic calculator apparatus comprising: a data memory including a plurality of data registers, each having an input terminal and an output terminal; a data output bus; a source of input data; memory output control means responsive to register output select information identifying one of said registers for coupling the output terminal thereof to said data output bus; memory input control means responsive to register input select information identifying one of said registers for coupling the input terminal thereof to said source of input data; a control memory having a plurality of addressable locations, each adapted to store a control word containing register output select information and register input select information; a program memory having a plurality of addressable locations adapted to store instructions including data modification instructions, each identifying one of said control memory locations; a program counter capable of defining a plurality of counts, each identifying a different one of said program memory locations; means responsive to said program counter for reading the instruction stored in the program memory location identified by the count defined by said program counter; means responsive to a data modification instruction read from said program memory for reading the control word stored in the control memory location identified by said data modification instruction; and means responsive to a control word read from said control memory for coupling the register output select information and the register input select information contained therein to said memory output control means and said memory input control means, respectively.
Claim 2
Dependent Claim
250 words
An electronic calculator apparatus comprising: a data memory including a plurality of data registers, each having an input terminal and an output terminal; a data output bus; a source of input data; memory output control means responsive to register output select information identifying one of said registers for coupling the output terminal thereof to said data output bus; memory input control means responsive to register input select information identifying one of said registers for coupling the input terminal thereof to said source of input data; a control memory having a plurality of addressable locations, each adapted to store a control word containing register output select information and register input select information; a program memory having a plurality of addressable locations adapted to store instructions including data modification instructions, each identifying one of said control memory locations; a program counter capable of defining a plurality of counts, each identifying a different one of said program memory locations; means responsive to said program counter for reading the instruction stored in the program memory location identified by the count defined by said program counter; means responsive to a data modification instruction read from said program memory for reading the control word stored in the control memory location identified by said data modification instruction; and means responsive to a control word read from said control memory for coupling the register output select information and the register input select information contained therein to said memory output control means and said memory input control means, respectively.
Claim 3
Dependent Claim
18 words
The apparatus of claim 1 wherein said control memory and said program memory each comprises a read-only memory.
Claim 4
Dependent Claim
85 words
The apparatus of claim 1 wherein said control word is comprised of a plurality of binary digits; and wherein said memory output control means includes a shift register and said memory input control means includes a shift register; and wherein said means for reading said control word includes means for serially providing the binary digits thereof to the input of one of said shift registers and for coupling the serial output from that shift register to the input of the other of said shift registers.
Claim 5
Dependent Claim
56 words
The apparatus of claim 1 wherein said means responsive to said data modification instruction includes an instruction register; means for entering instructions read from said program memory into said instruction register; and decoder means coupled to said instruction register and responsive to a data modification instruction entered therein for selecting a control memory location for reading.
Claim 6
Dependent Claim
17 words
The apparatus of claim 4 including timing means for periodically incrementing said program counter count by one.
Claim 7
Dependent Claim
46 words
The apparatus of claim 5 wherein said instructions adapted to be stored by said program memory include address modification instructions; and logic means coupled to said instruction register and responsive to an address modification instruction entered therein for modifying the count defined by said program counter.
Claim 8
Dependent Claim
76 words
The apparatus of claim 6 including a program count storage means; means responsive to at least one address modification instruction adapted to be entered into said instruction register for storing a count in said program count storage means related to the count defined by said program counter; and means responsive to at least one instruction adapted to be entered into said instruction register for recalling from said program count storage means the last count stored therein.
Claim 9
Dependent Claim
51 words
The apparatus of claim 1 including an adder having at least first and second inputs and an output; said source of input data including said adder output; and means respectively coupling the output terminal of one of said registers and said data output bus to said first and second adder inputs.
Claim 10
Dependent Claim
33 words
The apparatus of claim 8 including adder control means responsive to mode control information for controlling the operational characteristics of said adder; and wherein each of said control words includes mode control information.
Claim 11
Dependent Claim
51 words
The apparatus of claim 3 including an adder having at least first and second inputs and an output; said source of input data including said adder output; and means respectively coupling the output terminal of one of said registers and said data output bus to said first and second adder inputs.
Claim 12
Dependent Claim
65 words
The apparatus of claim 10 including adder control means responsive to mode control information for controlling the operational characteristics of said adder; and wherein each of said control words includes mode control information; said adder control means including a shift register; and means for coupling the serial output from said other of said shift registers to the input of said adder control means shift register.
Claim 13
Dependent Claim
165 words
An electronic calculator comprising: a plurality of keys, each adapted to be individually actuated to generate a unique multibit key code; compiler means including at least first and second registers, each adapted to store one of said multibit key codes, said compiler means including means for initially storing each generated key code in said first register; an output gating means; means coupling the outputs of said first and second registers to said output gating means; decode and logic means responsive to a first type of generated key code for causing said output gating means to pass the contents of said first register, and responsive to a second type of generated key code for transferring the contents of said first register to said second register and responsive to a third type of generated key code for causing said output gating means to pass the contents of said second register; an instruction register; and means coupling the output of said output gating means to said instruction register.
Claim 14
Dependent Claim
165 words
An electronic calculator comprising: a plurality of keys, each adapted to be individually actuated to generate a unique multibit key code; compiler means including at least first and second registers, each adapted to store one of said multibit key codes, said compiler means including means for initially storing each generated key code in said first register; an output gating means; means coupling the outputs of said first and second registers to said output gating means; decode and logic means responsive to a first type of generated key code for causing said output gating means to pass the contents of said first register, and responsive to a second type of generated key code for transferring the contents of said first register to said second register and responsive to a third type of generated key code for causing said output gating means to pass the contents of said second register; an instruction register; and means coupling the output of said output gating means to said instruction register.
Claim 15
Dependent Claim
29 words
The calculator of claim 12 wherein the bits of said key codes are passed by said output gate and transferred between said first and second registers in serial fashion.
Claim 16
Dependent Claim
42 words
The calculator of claim 12 wherein said decode and logic means is further responsive to each of a plurality of generated key codes of a fourth type for causing said output gating means to pass a code generic to said fourth-type codes.
Claim 17
Dependent Claim
44 words
The calculator of claim 14 including a program memory having a plurality of addressable locations, each adapted to store an instruction; means for selectively reading instructions from said program memory; and means for coupling instructions read from said program memory to said instruction register.
Claim 18
Dependent Claim
47 words
The calculator of claim 15 including a program counter capable of defining a plurality of counts, each identifying a different one of said program memory locations; and wherein said means for reading instructions from said program memory is responsive to the count defined by said program counter.
Claim 19
Dependent Claim
198 words
The calculator of claim 16 including: a data memory including a plurality of data registers, each having an input terminal and an output terminal; a data output bus; a source of input data; memory output control means responSive to register output select information identifying one of said registers for coupling the output terminal thereof to said data output bus; memory input control means responsive to register input select information identifying one of said registers for coupling the input terminal thereof to said source of input data; a control memory having a plurality of addressable locations, each adapted to store a control word containing register output select information and register input select information; said program memory adapted to store data modification instructions each identifying one of said control memory locations; means responsive to a data modification instruction read from said program memory for reading the control word stored in the control memory location identified by said data modification instruction; and means responsive to a control word read from said control memory for coupling the register output select information and the register input select information contained therein to said memory output control means and said memory input control means, respectively.
Claim 20
Dependent Claim
19 words
The calculator of claim 17 wherein said control memory and said program memory each comprises a read only memory.
Claim 21
Dependent Claim
85 words
The calculator of claim 17 wherein said control word is comprised of a plurality of binary digits; and wherein said memory output control means includes a shift register and said memory input control means includes a shift register; and wherein said means for reading said control word includes means for serially providing the binary digits thereof to the input of one of said shift registers and for coupling the serial output from that shift register to the input of the other of said shift registers.
Claim 22
Dependent Claim
131 words
An electronic calculator apparatus including: a program memory having a first read-only portion and a second alterable portion, each portion including a plurality of addressable locations each capable of storing an instruction code; program counter means capable of defining a plurality of different counts each uniquely identifying one of said addressable locations in said program memory; instruction register means; decoding means responsive to said program counter means for accessing an instruction coded from the location in said program memory uniquely identified by the count defined by said program counter means; means responsive to instruction codes accessed from said program memory for entering an instruction code into said instruction register means; and means responsive to an instruction code entered into said instruction register for modifying the count in said program counter means.
Claim 23
Dependent Claim
131 words
An electronic calculator apparatus including: a program memory having a first read-only portion and a second alterable portion, each portion including a plurality of addressable locations each capable of storing an instruction code; program counter means capable of defining a plurality of different counts each uniquely identifying one of said addressable locations in said program memory; instruction register means; decoding means responsive to said program counter means for accessing an instruction coded from the location in said program memory uniquely identified by the count defined by said program counter means; means responsive to instruction codes accessed from said program memory for entering an instruction code into said instruction register means; and means responsive to an instruction code entered into said instruction register for modifying the count in said program counter means.
Claim 24
Dependent Claim
40 words
The calculator apparatus of claim 20 including: a plurality of keys, each individually actuatable to generate a unique key code; and compiler logic means responsive to key codes applied thereto for entering an instruction code into said instruction register means.
Claim 25
Dependent Claim
46 words
The calculator apparatus of claim 21 wherein said means responsive to said instruction codes accessed from said program memory includes means for applying codes accessed from said program memory alterable portion to said compiler logic means for entering an instruction code into said instruction register means.
Claim 26
Dependent Claim
88 words
The calculator apparatus of claim 20 including: keyboard means having a plurality of keys each individually actuatable to generate signals manifesting a unique keyboard instruction code; storage means adapted to store keyboard instruction codes and internal instruction codes; means for reading said storage means to generate signals manifesting said stored keyboard and internal instruction codes; and means responsive to said signals generated by said keyboard means and means for reading for storing representations of the codes manifested by said signals in said alterable portion of said program memory.
Claim 27
Dependent Claim
47 words
The calculator apparatus of claim 23 wherein said means responsive to instruction codes Accessed from said program memory includes a compiler logic means responsive to keyboard instruction codes accessed from said program memory alterable portion for entering an internal level instruction code into said instruction register means.
Claim 28
Dependent Claim
199 words
The calculator apparatus of claim 20 including: a data memory including a plurality of data registers, each having an input terminal and an output terminal; a data output bus; a source of input data; memory output control means responsive to register output select information identifying one of said registers for coupling the output terminal thereof to said data output bus; memory input control means responsive to register input select information identifying one of said registers for coupling the input terminal thereof to said source of input data; a control memory having a plurality of addressable locations, each adapted to store a control word containing register output select information and register input select information; said program memory adapted to store data modification instructions each identifying one of said control memory locations; means responsive to a data modification instruction read from said program memory for reading the control word stored in the control memory location identified by said data modification instruction; and means responsive to a control word read from said control memory for coupling the register output select information and the register input select information contained therein to said memory output control means and said memory input control means, respectively.
Claim 29
Dependent Claim
88 words
The calculator apparatus of claim 25 including: keyboard means having a plurality of keys each individually actuatable to generate signals manifesting a unique keyboard instruction code; storage means adapted to store keyboard instruction codes and internal instruction codes; means for reading said storage means to generate signals manifesting said stored keyboard and internal instruction codes; and means responsive to said signals generated by said keyboard means and mans for reading for storing representations of the codes manifested by said signals in said alterable portion of said program memory.
Claim 30
Dependent Claim
47 words
The calculator apparatus of claim 26 wherein said means responsive to instruction codes accessed from said program memory includes a compiler logic means responsive to keyboard instruction codes accessed from said program memory alterable portion for entering an internal level instruction code into said instruction register means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-07-12 | 1975-01-11 | 1975-07-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-07-12 | 1979-01-11 | 1979-07-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-07-12 | 1983-01-11 | 1983-07-13 | $7700.00 | Window Closed / Lapsed |