Periphery-control-units switching device

Claim 2

For use in combination with a computer system comprised of at least two central processors and at least two peripheral units capable of performing, printing, readin, readout and storage functions, the improvement comprising: a periphery-control-units switching device being adapted to selectively interconnect said peripherals and said processors in a mutually exclusive fashion; a first plurality of processor trunk lines, each connecting an associated processor to said switching device; a second plurality of peripheral unit trunk lines, each connecting an associated peripheral unit to said switching device; said switching device being comprised of a plurality of groups of switch means; each switch means of each group being assigned to an associated processor whereby the switch means group assigned to each processor and forming one of said groups selectively connects the processor trunk line of its associated processor to the same peripheral unit trunk line; means cross coupling the switch means of the same group for preventing simultaneous coupling of their associated peripheral unit trunk line with their associated processors.

Claim 3

The device of claim 1 wherein each of said switch means is comprised of a bistable flip-flop having set and reset input terminals and having first and second output terminals for selectively generating switching and inhibit signals, respectively, so that said first and second output terminals respectively generate no switching signal and no inhibit signal when a reset signal is applied to said reset input; said means cross-coupling said switch means including means for cross-coupling the second outputs to the set inputs of switch means associated with the same peripheral unit trunk line to inhibit setting of one of the switch means when the other of the switch means has previously received a switching signal.

Claim 4

The device of claim 2 wherein gate means is provided for each switch means; said gate means having at least first and second inputs for receiving a switching signal from its associated processor and the second inhibit output signal of the switch means of a different switch means group which is associated with the same peripheral units trunk line and having an output coupled to said set input terminal for coupling a switching signal to said set input only in the absence of an inhibit signal.

Claim 5

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises a periphery-control-units switching device for selectively interconnecting said peripheral units to said processors, said switching device comprising: a pair of cross coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting the first and second outputs of its associated bistable means ON and OFF, respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively, upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said processors to said peripheral units; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that processor associated with the enabled gating means.

Claim 6

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises a periphery-control-units switching device for selectively interconnecting said peripheral units to said processors, said switching device comprising: a pair of cross coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting the first and second outputs of its associated bistable means ON and OFF, respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively, upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said processors to said peripheral units; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that processor associated with the enabled gating means.

Claim 7

The system of claim 1 further comprising means coupled between each pair of bistable means assigned for connecting the processors to the same peripheral unit to prevent simultaneous seizure of its associated peripheral unit by more than one central processor.

Claim 8

The system of claim 4 further comprising: means coupled between each central processor and the bistable means assigned thereto to enable a central processor to interrupt the control of a peripheral unit already under the control of another central processor, said means further including means for issuing an interrupt signal to the interrupted central processor.

Claim 9

The system of claim 4 further comprising priority control means coupled to each of said bistable means responsive to commands from only a preselected central processor for enabling one of said central processors to terminate an established connection between a central processor of lower priority and a peripheral unit by resetting the bistable means responsible for said established connection.

Claim 10

The system of claim 4 further comprising a pair of fourth gating means for each peripheral unit for transferring data from said peripheral unit to said processors; each gating means of each of said pairs of fourth gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of fourth gating means may be enabled during a given time interval to transfer data from only that peripheral unit associated with the enabled gating means.

Claim 11

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises a periphery-control-units switching device for selectively interconnecting said peripheral units to said processors, said switching device comprising: a pair of cross-coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting first and second outputs of its associated bistable means ON and OFF respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said peripheral unit to said processors; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that peripheral unit associated with the enabled gating means.

Claim 12

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises a periphery-control-units switching device for selectively interconnecting said peripheral units to said processors, said switching device comprising: a pair of cross-coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting first and second outputs of its associated bistable means ON and OFF respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said peripheral unit to said processors; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that peripheral unit associated with the enabled gating means.

Claim 13

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises first and second periphery-control-units switching devices for selectively interconnecting said peripheral units to said processors, each of said switching device comprising: a pair of cross-coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting the first and second outputs of its associated bistable means ON and OFF, respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively, upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said processors to said peripheral units; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that processor associated with the enabled gating means.

Claim 14

In a system comprising at least two central processors and at least two peripheral units capable of respectively performing printout, readin, readout and storage functions, wherein the improvement comprises first and second periphery-control-units switching devices for selectively interconnecting said peripheral units to said processors, each of said switching device comprising: a pair of cross-coupled bistable means each having first and second outputs, each being associated with each of said processors; each of said bistable means including: first input gating means for setting the first and second outputs of its associated bistable means ON and OFF, respectively when said first gating means receives a set signal from its associated processor and when the second output of the bistable means coupled thereto is in the OFF state; and second gating means for setting the first and second outputs of its associated bistable means OFF and ON respectively, upon receipt of a reset signal from its associated processor; a pair of third gating means for each peripheral unit for transferring data from said processors to said peripheral units; each gating means of each of said pairs of third gating means being enabled by a respective one of said cross-coupled bistable means whereby only one gating means of each pair of third gating means may be enabled during a given time interval to transfer data from only that processor associated with the enabled gating means.