Abstract A circuit arrangement for telephone exchange installations wherein messages of different length are divided according to their length into a number of corresponding code signals of constant information volume for transmission in series over the same transmission path and consist of equally large groups of code elements, and wherein, prior to the code signals of a message, a length indicating signal indicative of the length of the message is transmitted to indicate the number of code signals corresponding to the message. First counter means presettable to an initial position by the length indicating signal and controllable to switch forward in pulse manner to a first predetermined position are used in conjunction with second counter means synchronously dependent on the switching forward of the first counter means and responsive thereto to be switched forward out of a second predetermined position. The second counter means have control outputs assigned to its counting positions that control the transmission and reception of code signals transmitted in series over the same transmission path from and to circuits individually assigned thereto. A comparator is responsive to the first counter means when the latter attains the first predetermined position to test the position of the second counter means and the received length indicating signal with regard to agreement.
In a circuit arrangement for telephone exchange installations wherein messages of different length are divided according to their length into a number of corresponding code signals of constant information volume for transmission in series over the same transmission path (U2) and consist of equally large groups of code elements, and wherein, prior to the code signals of a message, a length indicating signal indicative of the length of the message is transmitted to indicate the number of code signals corresponding to the message, the improvement consisting of: first counter means (RZ7-RZ0) presettable to an initial position by the length indicating signal and a controllable switch forward in pulse manner to a first predetermined position; second counter means VZ0- VZ8) synchronously dependent on the switching forward of the first counter means (RZ7- RZ0) and responsive thereto to be switched forward out of a second predetermined position, the second counter means having control outputs assigned to its counting positions (BVT1- BVT7) to control the transmission and reception of code signals transmitted in series over the same transmission path (U2) from and to circuits individually assigned thereto (JS1- JS4 BS1BS4 in FIG. 2); and a comparator (VG) responsive to the first counter means (RZ7RZ0) attaining the first predetermined position to test the position of the second counter means (VZ0- VZ8) and the received length indicating signal with regard to agreement.
Claim 2
Dependent Claim
227 words
In a circuit arrangement for telephone exchange installations wherein messages of different length are divided according to their length into a number of corresponding code signals of constant information volume for transmission in series over the same transmission path (U2) and consist of equally large groups of code elements, and wherein, prior to the code signals of a message, a length indicating signal indicative of the length of the message is transmitted to indicate the number of code signals corresponding to the message, the improvement consisting of: first counter means (RZ7-RZ0) presettable to an initial position by the length indicating signal and a controllable switch forward in pulse manner to a first predetermined position; second counter means VZ0- VZ8) synchronously dependent on the switching forward of the first counter means (RZ7- RZ0) and responsive thereto to be switched forward out of a second predetermined position, the second counter means having control outputs assigned to its counting positions (BVT1- BVT7) to control the transmission and reception of code signals transmitted in series over the same transmission path (U2) from and to circuits individually assigned thereto (JS1- JS4 BS1BS4 in FIG. 2); and a comparator (VG) responsive to the first counter means (RZ7RZ0) attaining the first predetermined position to test the position of the second counter means (VZ0- VZ8) and the received length indicating signal with regard to agreement.
Claim 3
Dependent Claim
21 words
A circuit arrangement as recited in claim 1 further comprising: a storage means (S1- S7) to receive the length indicating signal.
Claim 4
Dependent Claim
30 words
A circuit arrangement as recited in claim 2 wherein the length indicating signal is transmitted by the storage means (S1-S7) to the first counter means (RZ7-RZ0) and the comparator (VG).