Data processing system input-output arrangement

Claim 2

A data processing system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; a data processor comprising first control means for generating and transmitting address signals to said buffer means to obtain said line status information and said input data from said buffer means, and second control means, responsive to signals generated by said first control means and operating contemporaneously with said first control means, for processing said input data, and for transmitting said output data to said buffer means in accordance with said line status information.

Claim 3

A data processing system in accordance with claim 1 wherein said data processor further comprises access control means for controlling access to said buffer means and for selectively allocating such access to said first and said second control means in accordance with a defined priority plan.

Claim 4

A data processing system in accordance with claim 1 wherein said first control means comprises means for generating a first control signal in accordance with said obtained line status information; and wherein said second control means comprises means responsive to said first control signal to commence said processing and transmitting of data and means for generating a second control signal upon the commencement of said processing and transmitting of data; said first control means comprising means responsive to said first control signal to halt said transmission of address signals to saiD buffer means and responsive to said second control signals to resume said transmission of address signals, said first control means generates and transmits address signals during periods of time in which said second control means independently processes said input data and transmits said output data.

Claim 5

A data processing system in accordance with claim 3 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information, and said input data from said first register means to said second register means.

Claim 6

A data processing system in accordance with claim 3 wherein: said line status information comprises line identification numbers; said first control means further comprises first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information, and said input data from said first register means to said second register means.

Claim 7

A data processing system in accordance with claim 1 wherein: said plurality of data lines comprises lines (Type A) having a low data transmission rate and lines (Type C) having a relatively higher data transmission rate; certain of said buffer means are associated with said lines having said low data rate and are responsive to certain of said address signals, and others of said buffer means are associated with said lines having said relatively higher data rate and are responsive to others of said address signals; and said first control means comprises means for periodically interrupting the generation and transmission of said certain address signals and for initiating transmission of said other address signals.

Claim 8

A data processing system in accordance with claim 1 wherein: said plurality of data lines comprises lines (Type A) having a first data rate, lines (Type B) having a second data rate, and lines (Type C) having a third data rate; said buffer means comprise first, second, and third buffer means uniquely associated with said lines having said first, second, and third data rates respectively, said first, second, and third buffer means being responsive to first, second, and third address signals respectively; and said first control means comprises: means for generating first and second timing signals, means for interrupting the generation and transmission of said first and said second address signals and for initiating the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of the transmission of a specified number of third address signals in an uninterrupted sequence, said means for interrupting being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.

Claim 9

A data switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means responsive to said command signals for transferring data between said main processor and said first memory means, second circuit means for transferring data between said first memory means and said second memory means, third circuit means for transferring data between said buffer means and said first memory means, and access control means for controlling access to said first memory means and for selectively allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.

Claim 10

A data switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means responsive to said command signals for transferring data between said main processor and said first memory means, second circuit means for transferring data between said first memory means and said second memory means, third circuit means for transferring data between said buffer means and said first memory means, and access control means for controlling access to said first memory means and for selectively allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.

Claim 11

A data switching system in accordance with claim 8 wherein said second circuit means comprises a plurality of transfer control means and a plurality of register means uniquely associated with said transfer control means, said plurality of transfer control means operating concurrently to control the transfer of data between said associated register means and said first memory means and between said associated register means and said second memory means, said third circuit means further comprising access control means for controlling access to said second memory means and for selectively allocating such access to each of said plurality of transfer control means in accordance with a defined priority plan.

Claim 12

A data switching system in accordance with claim 8 wherein said third circuit means comprises first control means for generating and transmitting address signals to said buffer means to obtain said line status information and said input data from said buffer means, and second control means, responsive to signals generated by said first control means and operating concurrently with said first control means, for processing said input data, and for transmitting said output date to said buffer means in accordance with said line status information.

Claim 13

A data switching system in accordance with claim 10 wherein said third circuit means further comprises access control means for controlling access to said buffer means and for selectively allocating such access to said first and said second control means in accordance with a defined priority plan.

Claim 14

A data switching system in accordance with claim 10 wherein: said plurality of data lines comprises lines having a first data rate, lines having a second data rate, and lines having a third data rate; said buffer means comprises corresponding first, second, and third buffer means uniquely associated with said lines having said first, second, and third data rates, and responsive to first, second, and third address signals, respectively; and said first control means comprises: means for generating first and second timing signals, means to interrupt the generation and transmission of said first and said second address signals and to initiate the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of generation and transmission of a specified number of said third address signals in sequence, said means for interrupting being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.

Claim 15

A data switching system in accordance with claim 10 wherein: said first control means comprises means for generating a first control signal in accordance with said line status information; said second control means comprises means responsive to said first control signal to commence said processing and transmitting of data, and means for generating a second control signal upon the commencement of said processing and transmitting of data; and said first control means further comprises means responsive to said first control signal to halt the transmission of said address signals, and responsive to said second control signal to resume the tranSmission of address signals, whereby said first control means generates and transmits address signals to said buffer means during periods of time in which said second control means processes said input data and transmits said output data.

Claim 16

A data switching system in accordance with claim 13 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer address information corresponding to said transmitted address signals, and input data obtained from lines defined by said identification numbers; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer address information and said system input data from said first register means to said second register means.

Claim 17

A message switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means for transferring data between said main processor and said first memory means in response to said command signals, second circuit means comprising a plurality of transfer control means and a corresponding plurality of register means, said transfer control means operating contemporaneously to control the transfer of data between said corresponding register means and said first memory means and between said corresponding register means and said second memory means, and access control means for controlling access to said second memory means and allocating such access in accordance with a defined priority plan, third circuit means comprising first control means for generating and transmitting address signals to said buffer means to obtain line status information and said input data therefrom, second control means, responsive to signals generated by said first control means and operating contemporaneously with said first control means, for processing said input data and for transmitting said output data to said buffer means, and access control means for controlling access to said buffer means and for allocating such access to said first and said second control means in accordance with a defined priority plan, timing means for supplying a plurality of timing pulses to said first, second, and third circuit means, and access control means for controlling access to said first memory means and for allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.

Claim 18

A message switching system comprising: a plurality of data lines; buffer means connected to said lines for recording line status information defining the functional activity of said lines and for storing input and output data associated with each of said lines; first memory means; second memory means; a main processor comprising means for generating and transmitting command signals; an auxiliary processor comprising: first circuit means for transferring data between said main processor and said first memory means in response to said command signals, second circuit means comprising a plurality of transfer control means and a corresponding plurality of register means, said transfer control means operating contemporaneously to control the transfer of data between said corresponding register means and said first memory means and between said corresponding register means and said second memory means, and access control means for controlling access to said second memory means and allocating such access in accordance with a defined priority plan, third circuit means comprising first control means for generating and transmitting address signals to said buffer means to obtain line status information and said input data therefrom, second control means, responsive to signals generated by said first control means and operating contemporaneously with said first control means, for processing said input data and for transmitting said output data to said buffer means, and access control means for controlling access to said buffer means and for allocating such access to said first and said second control means in accordance with a defined priority plan, timing means for supplying a plurality of timing pulses to said first, second, and third circuit means, and access control means for controlling access to said first memory means and for allocating such access to said first, second, and third circuit means in accordance with a defined priority plan.

Claim 19

A message switching system in accordance with claim 15 wherein said first control means comprises means for generating a first control signal in accordance with said line status information; and wherein said second control means comprises means responsive to said first control signals to commence said processing and transmitting of data, and means for generating second control signals upon the commencement of said processing and transmitting of data; said first control means comprising means responsive to said first control signal to halt the transmission of address signals, and to said second control signals to resume transmission of address signals, said first control means generates and transmits address signals during periods of time in which said second control means processes said input data and transmits said output data.

Claim 20

A message switching system in accordance with claim 16 wherein: said first control means further comprises means for generating line identification numbers in accordance with said line status information, and first register means for storing: said line identification numbers, buffer addresses corresponding to said transmitted address signals, and said input data; and said second control means comprises second register means and means responsive to said first control signal for transferring said line identification numbers, said buffer addresses, and said system input data from said first to said second register means.

Claim 21

A message switching system in accordance with claim 15 wherein: said plurality of data lines comprises lines (Type A) having a first data rate, lines (Type B) having a second data rate, and lines (Type C) having a third data rate; said buffer means comprises corresponding first, second, and third buffer means associated with said lines and responsive to first, second, and third address signals, respectively; said first control means comprises: means for generating first and second timing signals, and means for interrupting the generation and transmission of said first and said second address signals and for initiating the generation and transmission of said third address signals in response to said first timing signals, and means for generating completion signals upon completion of transmission of a specified number of said third address signals, said interrupting means being responsive to said completion signals and said second timing signals to selectively generate and transmit said first and said second address signals.

Claim 22

In combination: a plurality of data signal sources adapted to generate status signals representing the functional activity of said sources, memory means for storing a plurality of control words at predetermined address locations, register means for storing information representing the memory addresses defining said predetermined address locations, timing means for generating timed interrupt signals, scan control means responsive to said timed interrupt signals to obtain control words from memory locations defined by said memory addresses and to scan said sources in accordance with said obtained control words, to determine the functional activity of the sources defined by said control words, and means responsive to said timed interrupt signals for selectively altering the contents of said register means.

Claim 23

In combination: a plurality of data signal sources adapted to generate status signals representing the functional activity of said sources, memory means for storing a plurality of control words at predetermined address locations, register means for storing information representing the memory addresses defining said predetermined address locations, timing means for generating timed interrupt signals, scan control means responsive to said timed interrupt signals to obtain control words from memory locations defined by said memory addresses and to scan said sources in accordance with said obtained control words, to determine the functional activity of the sources defined by said control words, and means responsive to said timed interrupt signals for selectively altering the contents of said register means.

Claim 24

In combination: a data processor, a plurality of data handling devices connectable to said data processor, each of said devices being adapted to transmit input data to said data processor and to receive output data from said data processor in response to stimulation signals, first control means in said data processor for generating and transmitting said stimulation signals and for receiving said input data, and second control means, responsive to signals from said first control means and operating contemporaneously with said first control means, for processing said input data and transmitting said stimulation signals and said output data.

Claim 25

In combination: a data processor, a plurality of data handling devices connectable to said data processor, each of said devices being adapted to transmit input data to said data processor and to receive output data from said data processor in response to stimulation signals, first control means in said data processor for generating and transmitting said stimulation signals and for receiving said input data, and second control means, responsive to signals from said first control means and operating contemporaneously with said first control means, for processing said input data and transmitting said stimulation signals and said output data.