US3579122A
Expired / Lapsed
US
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Digital filter for reducing sampling jitter in digital control systems
Assignee: National Aeronautics and Space Administration
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Filing: 1969-12-23
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Granted: 1971-05-18
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Expires: 1989-12-23
Abstract
Abstract A digital filter comprising two up-down counters A and B. Counter A which is responsive to a sampled input signal which is quantized into three levels +1, -1 and 0, is incremented in response to each +1 input, decremented in response to each -1 input, and remains unchanged in response to a 0 input. Counter B, which includes N stages, is incremented at each sampling time when A is positive, decremented when A is negative and remains unchanged when A is zero. When B overflows in a positive direction A is decremented by one while a negative overflow of B results in A being incremented by one. The filter output is +2 N when A is positive, -2 N when A is negative and zero (0) when the count in A is zero.
Inventors
- 👤 Tage O Anderson
- 👤 William J Hurd
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 18:58
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0223; H03C; H03C3/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
58 words
A digital circuit comprising: a first up-down counter; a second up-down counter; and logic means for interconnecting said counters so that the count in said second counter is changed as a function of the count in said first counter and the count in said first counter is changed as a function of the overflow of said second counter.
Claim 2
Dependent Claim
58 words
A digital circuit comprising: a first up-down counter; a second up-down counter; and logic means for interconnecting said counters so that the count in said second counter is changed as a function of the count in said first counter and the count in said first counter is changed as a function of the overflow of said second counter.
Claim 3
Dependent Claim
107 words
The arrangement as recited in claim 1 wherein said second counter comprises an N-bit counter and said first counter is responsive to an input which is quantized to at least first and second levels and means for varying the count in said first counter in a first direction in response to a first level input and in a second direction in response to a second level input, and said logic means vary the count in said first direction when said second counter overflows in a first direction and vary the count in said counter in said second direction when said second counter overflows in a second direction.
Claim 4
Dependent Claim
101 words
The arrangement as recited in claim 1 wherein said logic means include means for incrementing the count in said second counter as long as the count in said first count differs from zero in a first direction, means for decrementing the count in said second counter when said count in said first counter differs from zero in a second direction, and said circuit further including means for decrementing the count in said first counter when said second counter overflows in a first direction and for incrementing the count in said first counter when said second counter overflows in a second direction.
Claim 5
Dependent Claim
62 words
The arrangement as recited in claim 3 wherein said first counter is responsive to an input which is quantized into at least first and second levels and said circuit includes means for incrementing the count in said first counter in response to a first level input and for decrementing the count in said first counter in response to a second level input.
Claim 6
Dependent Claim
71 words
The arrangement as recited in claim 4 wherein said second counter is incremented and decremented when the count in said first counter is positive and negative respectively with respect to a zero count and said first counter is decremented when said second counter overflows from a maximum count to a zero count and said first counter is incremented when said second counter overflows from a zero count to a maximum count.
Claim 7
Dependent Claim
53 words
The arrangement as recited in claim 5 wherein said first and second input levels represent positive and negative levels with respect to a zero level which represents a third input level and said circuit includes means for inhibiting said first counter from counting in either direction in response to a third level input.
Claim 8
Dependent Claim
61 words
The arrangement as recited in claim 6 wherein said second counter comprises an N-bit counter each of said first and second input levels being 1 amplitude unit, and said circuit further including means for providing an output having an amplitude which is +2 N, 0 or -2 N when the count in said first counter is positive, 0, or negative, respectively.
Claim 9
Dependent Claim
62 words
The arrangement as recited in claim 4 wherein said second counter is incremented and decremented when the count in said first counter is negative and positive respectively with respect to zero, and said first counter is incremented and decremented when said second counter overflows from a maximum count to a zero count and from a zero count to a maximum count respectively.
Claim 10
Dependent Claim
53 words
The arrangement as recited in claim 8 wherein said first and second input levels represent positive and negative levels with respect to a zero level which represents a third input level and said circuit includes means for inhibiting said first counter from counting in either direction in response to a third level input.
Claim 11
Dependent Claim
61 words
The arrangement as recited in claim 9 wherein said second counter comprises an N-bit counter each of said first and second input levels being 1 amplitude unit, and said circuit further including means for providing an output having an amplitude which is +2 N, 0 or -2 N when the count in said first counter is positive, 0, or negative, respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |