Method and apparatus for detecting and diagnosing computer error conditions

Claim 2

In a digital data processing system having a plurality of discrete units, a system for determining error conditions within any of the discrete units comprising: means for storing a test routine directed to a selected one of the discrete units, the test routine comprising a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases; means for serially executing the test cases of the routine in a predetermined order; and means for detecting the failure of all test cases within any test string of the routine.

Claim 3

In a Digital data processing system, an error determining system according to claim 1 in which the executing means executes all test cases of each test string prior to executing any test cases of a succeeding test string and in which test cases of strings having larger numbers of test cases are executed prior to test cases of strings having fewer numbers of test cases.

Claim 4

In a digital data processing system, an error determining system according to claim 2 in which the storing means stores test strings in a sequence such that test strings having larger numbers of test cases precede test strings having fewer numbers of test cases.

Claim 5

In a digital data processing system, an error determining system according to claim 3 in which the storing means comprises magnetic tape.

Claim 6

In a digital data processing system, an error determining system according to claim 3 in which the means for executing the test cases comprises: means for setting the selected discrete unit to a predetermined initial state; means for feeding a single clock pulse to the discrete unit; means for determining the resultant state of the discrete unit effected by the clock pulse; and means for comparing the resultant state with a predetermined expected state.

Claim 7

In a digital data processing system, an error determining system according to claim 5 in which: each test case comprises a plurality of commands, each command being represented by a plurality of binary digits; the storing means comprises magnetic tape; and the commands are stored on the magnetic tape in blocks such that each block contains an integral number of test cases.

Claim 8

In a digital data processing system, an error determining system according to claim 5 in which: the comparing means comprises an EXCLUSIVE OR circuit for comparing bits in corresponding bit positions of two sets of binary digits respectively representing the resultant and predetermined expected states of the selected discrete unit and for presenting signals indicative of the bit positions with respect to which the comparison fails.

Claim 9

In a digital data processing system, an error determining system according to claim 7 in which: each test case comprises a plurality of commands, each command being represented by a plurality of binary digits; and in which the comparing means further comprises: a masking circuit responsive to a particular command within each test case and to the signals provided by the comparing means for determining whenever the signals indicate failure with respect to a particular bit position identified by the command and for providing an error signal in response to such determination.

Claim 10

In a digital data processing system, an error determining system according to claim 8 in which the means for detecting test case failures comprises: a binary error element; and means operative during the first test case of each test string and responsive to the particular command and to the error signal for setting the error element to its first binary state.

Claim 11

In a digital data processing system, an error determining system according to claim 9 in which the means for detecting test case failures further comprises: means operative during each test case subsequent to the first test case of a test string and responsive to the particular command for resetting the error element to its second binary state in the absence of the error signal.

Claim 12

In a digital data processing system, an error determining system according to claim 10 further comprising: means responsive to the final command of each test case and to the error element being in its first binary state for providing a signal indicative of the detection of an error condition.

Claim 13

In a digital data processing system, an error determining system according to claim 10 further comprising: means responsive to the final command of the final test case of each test string and to the error element being in its first binary statE for providing a signal indicative of the diagnosis of an error condition.

Claim 14

In a digital data processing system having a plurality of discrete units, a system for determining error conditions within any of the discrete units comprising: means for storing a test routine directed to a selected one of the discrete units, the test routine comprising a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases, the test strings being sequenced within the routine such that test strings having larger numbers of test cases precede test strings having fewer numbers of test cases; each test case comprising a plurality of commands, each command being represented by a plurality of binary digits including operation code binary digits which identify the commands; means for serially executing the test cases of the routine comprising: decoding circuitry for decoding the operation code binary digits of each command and for presenting signals indicative of each unique command within the test routine; means including a first matrix circuit responsive to signals from the decoding circuit indicative of a particular first command for setting the selected discrete unit to an initial state identified by at least one binary digit within the command; means responsive to signals from the decoding circuit indicative of a particular second command for feeding a single clock pulse to the discrete units; means including a second matrix circuit responsive to signals from the decoding circuit indicative of a particular third command for storing in a compare register binary digits manifesting the resultant state of the selected discrete unit effected by the clock pulse; means including an EXCLUSIVE OR circuit responsive to signals from the decoding circuit indicative of a particular fourth command for comparing bits in corresponding bit positions of the compare register and a particular group of bit positions within the fourth command, bits in the latter bit positions manifesting the expected state of the selected discrete unit, and for providing signals indicative of the bit positions with respect to which the comparison failed; and means including a masking circuit responsive to signals from the decoding circuit indicative of a particular fifth command for determining whether the signals provided by the comparing means indicate a comparison failure with respect to a bit position identified by binary digits within the fifth command and for providing an error signal indicative of failure of a test case in response to such determination; and means for detecting the failure of all test cases within any test string of the routine.

Claim 15

In a digital data processing system having a plurality of discrete units, a system for determining error conditions within any of the discrete units comprising: means for storing a test routine directed to a selected one of the discrete units, the test routine comprising a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases, the test strings being sequenced within the routine such that test strings having larger numbers of test cases precede test strings having fewer numbers of test cases; each test case comprising a plurality of commands, each command being represented by a plurality of binary digits including operation code binary digits which identify the commands; means for serially executing the test cases of the routine comprising: decoding circuitry for decoding the operation code binary digits of each command and for presenting signals indicative of each unique command within the test routine; means including a first matrix circuit responsive to signals from the decoding circuit indicative of a particular first command for setting the selected discrete unit to an initial state identified by at least one binary digit within the command; means responsive to signals from the decoding circuit indicative of a particular second command for feeding a single clock pulse to the discrete units; means including a second matrix circuit responsive to signals from the decoding circuit indicative of a particular third command for storing in a compare register binary digits manifesting the resultant state of the selected discrete unit effected by the clock pulse; means including an EXCLUSIVE OR circuit responsive to signals from the decoding circuit indicative of a particular fourth command for comparing bits in corresponding bit positions of the compare register and a particular group of bit positions within the fourth command, bits in the latter bit positions manifesting the expected state of the selected discrete unit, and for providing signals indicative of the bit positions with respect to which the comparison failed; and means including a masking circuit responsive to signals from the decoding circuit indicative of a particular fifth command for determining whether the signals provided by the comparing means indicate a comparison failure with respect to a bit position identified by binary digits within the fifth command and for providing an error signal indicative of failure of a test case in response to such determination; and means for detecting the failure of all test cases within any test string of the routine.

Claim 16

In a digital data processing system, an error determining system according to claim 13 in which the determining means is also responsive to signals from the decoding circuit indicative of a particular sixth command for determining whether the signals provided by the comparing means indicate a comparison failure with respect to a particular bit position identified by binary digits within the sixth command and for providing an error signal indicative of failure of a test case in response to such determination.

Claim 17

In a digital data processing system, an error determining system according to claim 14 in which the first test case of each test string includes the particular fifth command and excludes the particular sixth command and all other test cases include the particular sixth command and exclude the particular fifth command.

Claim 18

In a digital data processing system, an error determining system according to claim 15 in which the means for detecting test case failures comprises: a binary error element; and means responsive to the signals from the decoding circuit indicative of the particular fifth command and to the error signal for setting the error element to its first binary state.

Claim 19

In a digital data processing system, an error determining system according to claim 16 in which the means for detecting test case failures further comprises means responsive to the signals from the decoding circuit indicative of the particular sixth command for resetting the error element to its second binary state in the absence of the error signal.

Claim 20

In a digital data processing system, an error determining system according to claim 17 further comprising means responsive to signals from the decoding circuit indicative of a particular seventh command, the particular seventh command being the final command of the final test case of each test string, and to the error element being in its first binary state for providing a signal indicative of the failure of every test case of a test string.

Claim 21

In a digital data processing system, an error determining system according to claim 18 in which the test routine contains a particular eighth command after predetermined ones of the test cases and further comprises: a normally ''''off'''' timing means; means responsive to signals from the decoding circuit indicative of either the particular fifth or sixth commands and to the timing means being ''''off'''' for turning the timing means ''''on, '''' the timing means remaining ''''on'''' for a predetermined period of time and providing a cycle signal while ''''on''''; and means responsive to signals from the decoding circuit indicative of the particular eighth command and to the cycle signal for causing the executing means to repeatedly reexecute the preceding test case until the timing means again turns ''''off.''''

Claim 22

In a digital data processing system, an error determining system according to claim 19 further comprising: a binary intermittent error element, the intermittent element normally being in its second binary state; and means responsive to the error signal, to the cycle signal and to the error element being in its second binary state for setting the intermittent error element to its first binary state.

Claim 23

In a digital data processing system, an error determining system according to claim 20 further comprising: means responsive to the cycle signal and to the error element being in its first binary state for setting the intermittent error element to its first binary state, in the absence of the error signal.

Claim 24

In a digital data processing system having a plurality of discrete units, a system for determining error conditions within any of the discrete units, comprising: means for storing a test routine directed to a selected one of the discrete units, the test routine comprising a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases; first binary error element; a second binary error element; means for serially executing the test cases of the routine in a predetermined order and for determining the success of such execution; means for causing the executing means to reexecute predetermined ones of the test cases a predetermined number of times prior to execution of the next succeeding test case; and means for establishing a first binary value in the first error element in response to the failure of every execution of every test case within any test string and for establishing a first binary value in the second error element in response to the failure of at least one but less than all executions of any test case.

Claim 25

In a digital data processing system having a plurality of discrete units, a system for determining error conditions within any of the discrete units, comprising: means for storing a test routine directed to a selected one of the discrete units, the test routine comprising a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases; first binary error element; a second binary error element; means for serially executing the test cases of the routine in a predetermined order and for determining the success of such execution; means for causing the executing means to reexecute predetermined ones of the test cases a predetermined number of times prior to execution of the next succeeding test case; and means for establishing a first binary value in the first error element in response to the failure of every execution of every test case within any test string and for establishing a first binary value in the second error element in response to the failure of at least one but less than all executions of any test case.

Claim 26

In a digital data processing system, an error determining system according to claim 22 in which the establishing means comprises: means for establishing the first binary value in the first error element in response to failure of the first execution of the first test case of any test string; and means for establishing the second binary value in the first error element in response to the success of the first execution of any succeeding test case of the test string.

Claim 27

In a digital data processing system, an error determining system according to claim 23 in which the establishing means further comprises: means for establishing the first binary value in the second error element in response to the success of the second or any subsequent execution of a test case, the first error element being in its first binary state.

Claim 28

In a digital data processing system, an error determining system according to claim 24 in which the establishing means further comprises: means for establishing the first binary value in the second error element in response to the failure of the second or any subsequent execution of a test case, the first error element being in its second binary state.

Claim 29

In a digital data processing system having a main memory, means for receiving digital words from an auxiliary storage device and for storing them into predetermined locations within the main memory, a unit comprising a plurality of flip-flop circuits, and means for reading digital words from the main memory, a system for determining error conditions within the unit comprising: first means coupled to the unit and responsive to a first ''''Scan-In'''' command word read from main memory for establishing, in flip-flop circuits identified by the command, initial conditions also identified by the command; second means coupled to the unit and responsive to a first ''''Test'''' command read from main memory for enabling transmission of a clock signal to the flip-flop circuits; third means responsive to a first ''''Scan-Out'''' command read from main memory for determining the resultant conditions in flip-flop circuits identified by the command; fourth means responsive to a first ''''Compare'''' command read from main memory for comparing the resultant conditions with predetermined conditions identified by the command; a bistable error element; fifth means responsive to a ''''Set Error'''' command read from main memory for setting the error element to a first bistable condition in response to failure of the preceding comparison; the first means also being responsive to a second ''''Scan-In'''' command word read from main memory for establishing in flip-flop circuits identified by the command initial conditions also identified by the command; the second means also being responsive to a second ''''Test'''' command read from main memory for again enabling transmission of a clock signal to the flip-flop circuits; the third means also being responsive to a second ''''Scan-Out'''' command read from main memory for determining the resultant conditions in flip-flop circuits identified by the command; the fourth means also being responsive to a second ''''Compare'''' command read from main memory for comparing the last-mentioned resultant conditions with predetermined conditions identified by the command; and sixth means coupled to the unit and responsive to a ''''Reset Error'''' command read from main memory for resetting the error element to its second bistable condition in response to the success of the preceding comparison.

Claim 30

In a digital data processing system having a main memory, means for receiving digital words from an auxiliary storage device and for storing them into predetermined locations within the main memory, a unit comprising a plurality of flip-flop circuits, and means for reading digital words from the main memory, a system for determining error conditions within the unit comprising: first means coupled to the unit and responsive to a first ''''Scan-In'''' command word read from main memory for establishing, in flip-flop circuits identified by the command, initial conditions also identified by the command; second means coupled to the unit and responsive to a first ''''Test'''' command read from main memory for enabling transmission of a clock signal to the flip-flop circuits; third means responsive to a first ''''Scan-Out'''' command read from main memory for determining the resultant conditions in flip-flop circuits identified by the command; fourth means responsive to a first ''''Compare'''' command read from main memory for comparing the resultant conditions with predetermined conditions identified by the command; a bistable error element; fifth means responsive to a ''''Set Error'''' command read from main memory for setting the error element to a first bistable condition in response to failure of the preceding comparison; the first means also being responsive to a second ''''Scan-In'''' command word read from main memory for establishing in flip-flop circuits identified by the command initial conditions also identified by the command; the second means also being responsive to a second ''''Test'''' command read from main memory for again enabling transmission of a clock signal to the flip-flop circuits; the third means also being responsive to a second ''''Scan-Out'''' command read from main memory for determining the resultant conditions in flip-flop circuits identified by the command; the fourth means also being responsive to a second ''''Compare'''' command read from main memory for comparing the last-mentioned resultant conditions with predetermined conditions identified by the command; and sixth means coupled to the unit and responsive to a ''''Reset Error'''' command read from main memory for resetting the error element to its second bistable condition in response to the success of the preceding comparison.

Claim 31

In a digital data processing system according to claim 26: a switch means, one position of the switch means indicating that error conditions are to be detected, another position of the switch means indicating that error conditions are to be diagnosed; and a seventh means responsive to an ''''End'''' command read from main memory and to the switch being in its one position for determining the status of the error element and for providing a signal in response to the error element being in its first bistable condition.

Claim 32

In a digital data processing system according to claim 27: an eighth means responsive to an ''''End String'''' command read from main memory and to the switch being in its other position for determining the status of the error element and for providing a signal in response to the error element being in its first bistable condition.

Claim 33

In a programmable digital data processing system having a plurality of discrete units, a method for determining error conditions within any of the discrete units under program control of the data processing system, the steps comprising: storing a program test routine directed to a selected one of the discrete units, the test routine having a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases; executing serially the test cases of the routine in a predetermined order; detecting the success or failure of each such test case execution; and detecting the failure of all test cases within a single test string.

Claim 34

In a programmable digital data processing system having a plurality of discrete units, a method for determining error conditions within any of the discrete units under program control of the data processing system, the steps comprising: storing a program test routine directed to a selected one of the discrete units, the test routine having a plurality of test cases which are grouped into a plurality of test strings, each string including one or more test cases; executing serially the test cases of the routine in a predetermined order; detecting the success or failure of each such test case execution; and detecting the failure of all test cases within a single test string.

Claim 35

In a programmable digital data processing system, a method of determining error conditions according to claim 29 wherein the executing step comprises: setting the selected discrete unit to a predetermined initial state; feeding a clock pulse to the selected discrete unit; observing the actual resultant state of the selected discrete unit effected by the clock pulse; and comparing the observed resultant state with a predetermined expected resultant state.

Claim 36

In a programmable digital data processing system, a method of determining error conditions according to claim 30 wherein the storing step comprises: arranging the test cases such that test cases of strings having larger numbers of test cases are executed prior to test cases of strings having fewer numbers of test cases.

Claim 37

In a programmable digital data processing system, a method of determining error conditions according to claim 31 in which the comparing step comprises: comparing bits in corresponding bit positions of two sets of binary digits respectively representing the actual resultant and predetermined resultant states; and indicating the bit positions with respect to which the comparison failed.

Claim 38

In a programmable digital data processing system, a method of determining error conditions according to claim 32 in which the step of detecting success comprises: masking predetermined ones of the bit positions; and providing error signals representative of unmasked ones of the bit positions with respect to which the comparison failed, the error signals being indicative of failure of the test cases.

Claim 39

In a programmable digital data processing system, a method of determining error conditions according to claim 33 in which the step of detecting failure comprises: setting a first binary error element to a first binary state in response to an error signal occurring during the first test case of any test string; and resetting the first binary error element to its second binary state in the absence of an error signal occurring during any test case of a test string subsequent to the first test case of the string.

Claim 40

In a programmable digital data processing system, a method of determining error conditions according to claim 34 further comprising: repeatedly executing predetermined ones of the test cases a predetermined number of times; and setting a second binary error element to its first binary state in response to detection of inconsistent results during the repeated execution of a single test case.

Claim 41

In a digital data processing system having circuits comprised of bistable devices controlled by clock pulses and a series of gating devices, system for determining errors in said circuits comprising: means for storing test strings each comprising a series of test cases; means for serially executing the test cases in each test string including means for setting at least one such bistable device to a predetermined state and for applying a clock pulse to such bistable devices; means for detecting the presence of an error in the state of at least one bistable device after such clock pulse in all test cases in a test string.

Claim 42

In a digital data processing system having circuits comprised of bistable devices controlled by clock pulses and a series of gating devices, system for determining errors in said circuits comprising: means for storing test strings each comprising a series of test cases; means for serially executing the test cases in each test string including means for setting at least one such bistable device to a predetermined state and for applying a clock pulse to such bistable devices; means for detecting the presence of an error in the state of at least one bistable device after such clock pulse in all test cases in a test string.

Claim 43

In a digital data processing system according to claim 36 wherein said means for detecTing comprises means settable to a first state in response only to an error in the first test case of a test string and settable to a second state in response to the lack of a failure in any test case in a test string subsequent to the first.

Claim 44

In a digital data processing system according to claim 37 wherein said test string comprises an end of string command at the end of each of said test strings and means for providing a predetermined output signal indicative of an error condition upon encountering said end of string command when said settable means is in said first state.