Time division multiplex system

Claim 2

A time division multiplex system for transmitting information from a transmitting point to a receiving point over a link at a predetermined rate comprising: a. a plurality of sources of input data, b. a plurality of transmission channels each associated with a different one of said sources and extending over said link, said transmission channels each having input and output channel portions respectively at said transmitting point and at said receiving point, said input channels each including a plurality of successive buffer registers and said output channels each including another plurality of successive buffer registers, and means for transferring said data between said successive registers, c. means in each of said input channels for controlling the rate of data transmission through the buffer registers thereof, so as to maintain said rate at said predetermined link rate, said rate controlling means including means for presetting coordination data in at least one of said input channel buffer registers, d. means connected to each of said input channels for transferring said coordination data together with said data from said sources from the last of said buffer registers thereof into said link and means connected to each of said output channels for the transferring of said coordination data and said information data from said sources from said link into the first of said successive buffer registers of said output channels, and e. means in each of said output channels responsive to said coordination data stored in at least one of said buffer registers thereof for controlling the rate of transmission of out data therefrom.

Claim 3

A time division multiplex system comprising: a. a plurality of input channels and a plurality of corresponding output channels connected at opposite ends of a data link and providing a plurality of data transmission channels, each of said input channels including means for storing data, separate means in said output channels also for storing said data, b. means in each of said input channels for transferring input information data through each of said input channel storing means to said link at a predetermined rate, c. means in each of said input channels for storing fill data in said storing means of each input channel when said input data is applied to said input channels at slower than said given rate, d. means in said output channels for applying said information data and said fill data received across said link from their corresponding input channels to said output channel storing means, and e. a plurality of means each corresponding to a different one of said output channels and responsive to said fill data stored therein for controlling the rate at which data is read out of said output channel storing means of the one of said output channels corresponding thereto.

Claim 4

A time division multiplex system comprising: a. a plurality of input channels and a plurality of corresponding output channels connected at opposite ends of a data link and providing a plurality of data transmission channels, each of said input channels including means for storing data, separate means in said output channels also for storing said data, b. means in each of said input channels for transferring input information data through each of said input channel storing means to said link at a predetermined rate, c. means in each of said input channels for storing fill data in said storing means of each input channel when said input data is applied to said input channels at slower than said given rate, d. means in said output channels for applying said information data and said fill data received across said link from their corresponding input channels to said output channel storing means, and e. a plurality of means each corresponding to a different one of said output channels and responsive to said fill data stored therein for controlling the rate at which data is read out of said output channel storing means of the one of said output channels corresponding thereto.

Claim 5

A time division multiplex system comprising: a. a plurality of corresponding input and output channels adapted to be connected to opposite ends of a data transmission link over which data is communicated serially at a certain rate, each of said plurality of corresponding input and output channels and said link providing a separate one of a plurality of data transmission channels for separate sources of data, b. Each of said input channels having a first plurality of successive data character storage registers, each of said output channels having a second plurality of successive data character registers, c. each of said input channels also including means for transferring said data into the first and out of the last of said first plurality of registers thereof at said certain rate and between said successive registers at a transfer rate equal to the quotient of the number of bits in said character and said certain rate, d. means for inserting a coordination character into one of said first plurality of input channel registers when input data is not applied thereto at said transfer rate, e. each of said output channels also including means for detecting said coordination characters in one of said registers of said second plurality of registers therein and inhibiting the transfer of said coordination characters between said one register and the next succeeding register of said second plurality of registers in its said output channel, and f. means also included in each of said output channels responsive to the rate at which said coordination characters are detected for controlling the rate at which data is outputted from the last of said output channel registers.

Claim 6

A time division multiplex system comprising: a. a plurality of corresponding input and output channels adapted to be connected to opposite ends of a data transmission link over which data is communicated serially at a certain rate, each of said plurality of corresponding input and output channels and said link providing a separate one of a plurality of data transmission channels for separate sources of data, b. Each of said input channels having a first plurality of successive data character storage registers, each of said output channels having a second plurality of successive data character registers, c. each of said input channels also including means for transferring said data into the first and out of the last of said first plurality of registers thereof at said certain rate and between said successive registers at a transfer rate equal to the quotient of the number of bits in said character and said certain rate, d. means for inserting a coordination character into one of said first plurality of input channel registers when input data is not applied thereto at said transfer rate, e. each of said output channels also including means for detecting said coordination characters in one of said registers of said second plurality of registers therein and inhibiting the transfer of said coordination characters between said one register and the next succeeding register of said second plurality of registers in its said output channel, and f. means also included in each of said output channels responsive to the rate at which said coordination characters are detected for controlling the rate at which data is outputted from the last of said output channel registers.

Claim 7

The invention as set forth in claim 3 including means in each of said input channels coupled to said input channel registers responsive to the data character stored in its immediately preceding input channel registers for reducing the number of bits in said data character and applying said reduced number of bit characters to said one input channel register, and means in each of said output channels connected to one of said output channels registers for translating said reduced bit characters into a format corresponding to the data characters stored in said immediately preceding input channel register.

Claim 8

The information as set forth in claim 4 including a source of timing signals associated with said plurality of output channels and wherein said coordination character responsive means includes means responsive to said timing signals for producing pulses having a variable repetition rate, means responsive to the rate at which said coordination characters are detected and said repetition rate of said pulses for deriving an error signal, and means responsive to said error signal for varying the repetition rate of said pulses, and means utilizing said pulses for reading said data characters out of the last of said output channel registers.

Claim 9

The invention as set forth in claim 5 wherein said reading out means includes output control logic including first logic means responsive to said pulses for producing timing pulses each in a separate one of a plurality of sequential timing intervals, said intervals each corresponding to a successive bit of said format, and second logic means connected to the last of said output channel registers and controlled by said timing pulses for reading out the bits of the data character stored therein sequentially in said sequential timing intervals whereby also to reconstitute said format.

Claim 10

The invention as set forth in claim 6 wherein said means for producing pulses having a variable rate comprises counting means, a plurality of gates coupled to said counting means each for resetting the counting means at different counts when enabled and for producing said timing pulses during different ones of said counts, an analog-to-digital converter for producing codes corresponding to different ones of said gates in accordance with the level of said error signal, and means connecting said converter to said gates for enabling a different one of said gates when said converter produces the code corresponding thereto for enabling different ones of said gates.

Claim 11

The invention as set forth in claim 6 wherein said first logic means of said output control logic includes a counter for counting said pulses, a decoder coupled to said counter for producing said timing pulses, each when said counter reaches a different successive counting state, and said second logic means includes a parallel to serial code converter having its parallel inputs coupled to said decoder and to said last register for reading said bits out of said register in different ones of said intervals selected.

Claim 12

The invention as set forth in claim 3 including a source of timing signals associated with said input channels, means for generating commutation pulses each corresponding to a different one of said input channels and sync characters in response to said timing signals; wherein said transferring means includes means for shifting input data serially into said first register, means for transferring data in parallel from said first register to said second register when said first register is full, means for transferring data from said second register to said third register at a said transfer rate and when said third register is empty, means under control of said timing signals and said commutation pulses for shifting data serially out of said third register; and wherein said inserting means includes means for presetting a fill character having a predetermined code in said second register immediately after the commutation pulse corresponding to said channel whereby the rate of data transfer out of said third register is maintained at said certain rate.

Claim 13

The invention as set forth in claim 9 including means responsive to said commutation pulses for inhibiting the transfer of data between said second and said third registers in each of said input channels during the period of its corresponding commutation pulse.

Claim 14

The invention as set forth in claim 9 including interlace logic responsive to the outputs of the third registers in each of said input channels and to said sync character for providing a serial stream of data to said link.

Claim 15

The invention as set forth in claim 11 including a source of timing signals associated with said output channels, means responsive to said output channel timing signals for producing a sequence of decommutation pulses each corresponding to a different one of said output channels, means for decoding said sync character, and means for inhibiting the generation of said decommutation pulses until said sync character is decoded.

Claim 16

The invention as set forth in claim 3 wherein said plurality of registers in each of said output channels comprise at least a first, a second and a third register; wherein said coordination character detection means includes means coupled to said first output channel register for decoding said coordination characters and providing an output when each said coordination character is decoded, means for transferring data from said first output channel register to said second output channel register when said first register is full and said second output channel register is empty, means responsive to said coordination character decoding means output for inhibiting the transfer of coordination characters to said second output channel register, means for transferring data from said second register to said third register when said third register is empty; and wherein said detected coordination character responsive means includes means for generating signals for reading out said third output register and enabling the transfer of data from said second to said third output channel register.

Claim 17

The invention as set forth in claim 13 including means operated by said third output channel register reading out signal generating means for presetting a special data character representing the presence of coordination characters and thereby the presence of transmission errors in one of said second and third output channel registers immediately after read out of data therefrom.