Patent US1929692A successfully refreshed from Google Patents.
US3575554A
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Frame synchronizer for a biorthogonal decoder
Assignee: International Telecommunications Satellite Organization
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Filing: 1968-04-16
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Granted: 1971-04-20
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Expires: 1988-04-16
Abstract
Abstract An 8-bit word having good autocorrelation properties is recirculated through an eight stage shift register at a receiving station to simultaneously generate the eight phases of the word. At the same time, a sending station having an 8-bit frame length transmits a repeating sequence of the same word. The transmitted word, now corrupted by channel noise, is then correlation detected with the eight phases of itself generated at the receiving station. The phase producing the largest correlation output is selected as the synchronized phase or frame, and is used to generate framing pulses during the subsequent data transmission.
Inventors
- 👤 William G Schmidt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 16:23
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/041; H04L7/042; H04L7/046
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
155 words
A frame synchronization system for an orthogonal decoder having an n bit frame length and including a correlation detector having first and second groups of n input terminals and n output terminals, comprising: a. means for receiving an incoming burst signal including a data portion preceded by a repeated sequence of an n bit word having good aUtocorrelation properties, b. means for individually applying the signal to the first group of input terminals of the correlation detector, c. means for simultaneously generating each of the possible phases of the word, d. means for individually applying the generated phases to the second group of input terminals of the correlation detector, and e. means responsive to a signal on one of the n output terminals of the correlation detector identifying the generated phase of the word that is in phase with the received word for generating a frame synchronization pulse at the beginning of each framing period.
Claim 2
Dependent Claim
155 words
A frame synchronization system for an orthogonal decoder having an n bit frame length and including a correlation detector having first and second groups of n input terminals and n output terminals, comprising: a. means for receiving an incoming burst signal including a data portion preceded by a repeated sequence of an n bit word having good aUtocorrelation properties, b. means for individually applying the signal to the first group of input terminals of the correlation detector, c. means for simultaneously generating each of the possible phases of the word, d. means for individually applying the generated phases to the second group of input terminals of the correlation detector, and e. means responsive to a signal on one of the n output terminals of the correlation detector identifying the generated phase of the word that is in phase with the received word for generating a frame synchronization pulse at the beginning of each framing period.
Claim 3
Dependent Claim
34 words
A frame synchronization system as defined in claim 1 wherein the means recited in subparagraph (c) comprises a recirculating shift register having n stages originally loaded with one of the phases of the word.
Claim 4
Dependent Claim
49 words
A frame synchronization system as defined in claim 2 wherein the means recited in subparagraph (e) of claim 1 comprises a decoder that produces an output pulse whenever the first bit of the in phase sequence of the word is in the register stage identified by the correlation detector.
Claim 5
Dependent Claim
38 words
A frame synchronization system as defined in claim 1 further comprising means for initiating the generating means recited in subparagraph (c) and enabling the applying means recited in subparagraph (d) in response to the acquisition of clock pulses.
Claim 6
Dependent Claim
37 words
A frame synchronization system as defined in claim 2 further comprising means for loading the shift register and enabling the applying means recited in subparagraph (d) of claim 1 in response to the acquisition of clock pulses.
Claim 7
Dependent Claim
31 words
A frame synchronization system as defined in claim 1 further comprising means for resetting the correlation detector to receive the data portion of the burst signal after a predetermined time delay.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-19 | 1974-10-19 | 1975-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-19 | 1978-10-19 | 1979-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-19 | 1982-10-19 | 1983-04-20 | $7700.00 | Window Closed / Lapsed |