US3573751A
Expired / Lapsed
US
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Fault isolation system for modularized electronic equipment
Assignee: GTE Sylvania Inc
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Filing: 1969-04-22
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Granted: 1971-04-06
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Expires: 1989-04-22
Abstract
Abstract A system for isolating faulty circuit modules in electronic equipment by the use of binary signature waveforms. All binary waveforms are partitioned into a selected number of classes by sampling each waveform at a predetermined synchronous rate to provide a series of binary sample values, forming n-bit binary numbers from successive n-bit groups of sample values, and summing, modulo N, all the n-bit binary numbers so formed during a predetermined interval, the remainder of said modulo N summation being used as a class identifier. To isolate circuit failures, each module is energized to generate a signature waveform which is analyzed to determine its class identifier. This analyzed class identifier is then compared with the stored class identifier of the correct signature waveform for that module, and a disagreement therebetween indicates a faulty circuit. Apparatus for isolating faults in this manner comprises a memory for storing the predetermined correct signature waveform class identifiers for each of the circuit modules, an n-bit accumulator for forming and summing the n-bit binary numbers from the signature sample values, a digital comparator for comparing the n-bit outputs of the memory and accumulator, and a test sequencer for selectively connecting a signature waveform from each of the circuit modules to the load input of the accumulator and selectively reading out from the memory a binary number which is the correct class identifier for the module from which a signature waveform is being obtained for analysis.
Inventors
- 👤 William E Delisle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 09:22
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/273; G06F11/277
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
115 words
A method for isolating faults in an electrical system having a plurality of interconnected circuits comprising the steps of: partitioning of waveforms into a selected number of classes each having an identifier; determining the identifier of a signature waveform for each of said circuits, which waveform represents proper operation of that circuit; storing the predetermined signature waveform class identifier for each of said circuits; energizing each of said circuits to generate a signature waveform; analyzing the signature waveform generated by each of said circuits to determine the class identifier corresponding thereto; and comparing the analyzed class identifier for each circuit with the stored class identifier for that circuit, a disagreement therebetween indicating a faulty circuit.
Claim 2
Independent Claim
115 words
A method for isolating faults in an electrical system having a plurality of interconnected circuits comprising the steps of: partitioning of waveforms into a selected number of classes each having an identifier; determining the identifier of a signature waveform for each of said circuits, which waveform represents proper operation of that circuit; storing the predetermined signature waveform class identifier for each of said circuits; energizing each of said circuits to generate a signature waveform; analyzing the signature waveform generated by each of said circuits to determine the class identifier corresponding thereto; and comparing the analyzed class identifier for each circuit with the stored class identifier for that circuit, a disagreement therebetween indicating a faulty circuit.
Claim 3
Dependent Claim
50 words
The method of claim 1 wherein said waveforms are binary waveforms, and said partitioning of the waveforms comprises the steps of: summing, modulo N, selected characteristic occurrences of said binary waveforms during a predetermined interval, where N is a predetermined positive integer; and using the remainder as said class identifier.
Claim 4
Dependent Claim
83 words
The method of claim 2 wherein said analyzing of the signature waveform generated by each of said circuits comprises the steps of: sampling said signature waveform at a predetermined rate to provide a series of binary sample values; forming n-bit binary numbers from successive n-bit groups of said sample values, each of said n-bit binary numbers representing the value of a respective n-bit group of samples; and summing, modulo N, the values of all n-bit groups of samples provided during said predetermined interval.
Claim 5
Dependent Claim
86 words
A fault isolation system for electrical equipment having a plurality of interconnected circuits comprising, in combination, means for storing a predetermined signature waveform class identifier for each of said circuits, means for obtaining a signature waveform from each of said circuits, means for analyzing the signature waveform obtained from each of said circuits to determine the class identifier corresponding thereto, and means for comparing the analyzed class identifier for each circuit with the stored class identifier for that circuit, a disagreement therebetween indicating a faulty circuit.
Claim 6
Dependent Claim
86 words
A fault isolation system for electrical equipment having a plurality of interconnected circuits comprising, in combination, means for storing a predetermined signature waveform class identifier for each of said circuits, means for obtaining a signature waveform from each of said circuits, means for analyzing the signature waveform obtained from each of said circuits to determine the class identifier corresponding thereto, and means for comparing the analyzed class identifier for each circuit with the stored class identifier for that circuit, a disagreement therebetween indicating a faulty circuit.
Claim 7
Dependent Claim
72 words
A fault isolation system in accordance with claim 4 wherein said means for analyzing the signature waveform obtained from each of said circuits comprises, means for sampling said signature waveform, and means for summing, modulo N, the output of said sampling means during a predetermined interval, where N is a predetermined positive integer, and where the remainder of said modulo N summation is the class identifier corresponding to said analyzed signature waveform.
Claim 8
Dependent Claim
118 words
A fault isolation system in accordance with claim 4 wherein: said stored waveform class identifier is an n binary number; each of said signatures is a binary waveform; and said means for analyzing the signature waveform obtained from each of said circuits comprises, means for sampling said signature waveform at a predetermined rate to provide a series of binary sample values, and means for forming and summing, modulo N, n binary numbers from successive n groups of said sample values during a predetermined interval, where N is a predetermined positive integer, and where the remainder of said modulo N summation, in the form of an n binary number, is the class identifier corresponding to said analyzed signature waveform.
Claim 9
Dependent Claim
34 words
A fault isolation system in accordance with claim 6 wherein said class identifier storage means comprises a memory from which any one of a plurality of n binary numbers may be selectively read out.
Claim 10
Dependent Claim
56 words
A fault isolation system in accordance with claim 7 wherein said means for forming and summing n binary numbers comprises an n accumulator, and said means for obtaining a signature waveform includes means for selectively connecting a signature waveform output of each of said circuits to the load input of said accumulator in a predetermined sequence.
Claim 11
Dependent Claim
38 words
A fault isolation system in accordance with claim 8 wherein said accumulator includes an n-bit shift register, and said sampling means comprises means for applying a stream of pulses at said predetermined rate to drive said shift register.
Claim 12
Dependent Claim
80 words
A fault isolation system in accordance with claim 9 further including means for selectively reading out from said memory an n-bit binary number which is the class identifier for the circuit from which a signature waveform is being obtained for analysis, said selective readout being substantially synchronous with said means for selectively connecting signature waveforms to said accumulator, and wherein said means for obtaining a signature further includes means for energizing each of said circuits to generate a signature waveform.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |