Programmable timing controls for magnetic memories

Claim 2

For use in a programmable data processing system including processing means and memory devices, programmable read-probe pulse selection circuitry for selectively controlling the times of occurrence of read-probe pulses employed to read data signals from a given one of said memory devices comprising: receiving means for receiving programmably alterable function signal groupings from said processing means, predetermined ones of said function signal groupings indicative of the programmably selectable times of occurrence of read-probe pulses for use in the control of the readout of data signals from said given one of said memory devices function decoder means coupled to said receiving means for providing read-probe pulse seleCtion signals in response to said predetermined ones of said function signal groupings; and gating means coupled to said function decoder means for selectively gating signals from said given one of said memory devices at predetermined times in response to said read-probe pulse selection signals.

Claim 3

Programmable read-probe pulse selection circuitry as in claim 1 wherein said receiving means includes storage register means for at least temporarily storing said programmably alterable function signal groupings, said storage register means including a plurality of bistable stages, each of said stages having true and complement output terminals for providing true and complement output signals indicative of the state of respective ones of the signals in said function signal groupings.

Claim 4

Programmable read-probe pulse selection circuitry as in claim 2 wherein said function decoder means includes first selection means coupled to a first group of predetermined ones of said stages for providing first selection signals identifying said predetermined ones of said functional signal groupings; and second selection means coupled to said first selection means and to a second group of predetermined ones of said stages for providing read-probe pulse selection signals in response to said function signal groupings.

Claim 5

Programmable read-probe pulse selection circuitry as in claim 3 wherein said gating means includes timing means coupled to said second selection means for providing programmably selected read-probe pulses for said gating of data signals at the programmably selected times in response to said read-probe pulse selection signals.

Claim 6

Programmable read-probe pulse selection circuitry as in claim 3 wherein said times of occurrence of said read-probe pulses include at least normally-timed read-probe pulses, early-timed read-probe pulses and late-timed read-probe pulses separately selectable by associated ones of said predetermined ones of said function signal groupings, and said second selection means includes early read-probe pulses selection means for providing early read-probe pulse selection signals, normal read-probe pulse selection means for providing normal read-probe pulse selection signals, and late read-probe pulse selection means for providing late read-probe pulse selection signals.

Claim 7

Programmable read-probe pulse selection circuitry as in claim 5 wherein said gating means includes first timing means coupled to said early read-probe pulse selection means for generating read-probe pulses a predetermined time earlier than normally-timed read-probe pulses in response to said early read-probe pulse selection signals, second timing means for generating said normally-timed read-probe pulses in response to said normal read-probe pulse selection signals, and third timing means for generating read-probe pulses a predetermined time later than said normally-timed read-probe pulses in response to said late read-probe pulse selection signals.

Claim 8

An improved programmably alterable memory timing system including: programmably alterable read-probe pulse generating means; magnetic memory means having addressable reading means for reading recorded signals from said memory means, output means for transmitting the recorded signals read from said memory means, and read-probe gating means coupled to said reading means and to said programmably alterable read-probe pulse-generating means for controlling transmission of said recorded signals read from said output means in response to pulses from said programmably alterable read-probe pulse-generating means; control means having first input means for receiving programmably alterable function signal groupings, a predetermined one of said function signal groupings controlling said source of read-probe pulses, second input means coupled to said output means for receiving said signals read from said magnetic memory means, error-detecting means coupled to said second input means for detecting and identifying erroRs in said signals read from said magnetic memory means, and function decoder means coupled to said first input means for providing read-probe pulse selection signals in response to said predetermined one of said function signal groupings; and means coupling said function decoder means to said programmably alterable read probe pulse generating means such that selectively timed read-probe pulses are applied to said read-probe gating means in response to said read-probe pulse selection signals.

Claim 9

An improved programmably alterable memory timing system including: programmably alterable read-probe pulse generating means; magnetic memory means having addressable reading means for reading recorded signals from said memory means, output means for transmitting the recorded signals read from said memory means, and read-probe gating means coupled to said reading means and to said programmably alterable read-probe pulse-generating means for controlling transmission of said recorded signals read from said output means in response to pulses from said programmably alterable read-probe pulse-generating means; control means having first input means for receiving programmably alterable function signal groupings, a predetermined one of said function signal groupings controlling said source of read-probe pulses, second input means coupled to said output means for receiving said signals read from said magnetic memory means, error-detecting means coupled to said second input means for detecting and identifying erroRs in said signals read from said magnetic memory means, and function decoder means coupled to said first input means for providing read-probe pulse selection signals in response to said predetermined one of said function signal groupings; and means coupling said function decoder means to said programmably alterable read probe pulse generating means such that selectively timed read-probe pulses are applied to said read-probe gating means in response to said read-probe pulse selection signals.

Claim 10

An improved programmably alterable memory timing system as in claim 7 and further including programmable data processor means coupled to said first input means in said control means for providing programmably alterable function signal groupings, and means responsively coupled to said error detecting means for programmably altering the selection of the ones of said function signal groupings to be applied to said control means for attempting to read the recorded signals correctly.

Claim 11

An improved programmably alterable memory timing system as in claim 8 wherein said input means includes storage register means for at least temporarily storing said programmably alterable function signal groupings, said storage register means including a plurality of bistable stages, each of said stages having true and complement output terminals for providing true and complement output signals indicative of the state of respective ones of the signals in said function signal groupings.

Claim 12

An improved programmably alterable memory-timing system as in claim 9 wherein said function decoder means includes first selection means coupled to a first group of predetermined ones of said stages for providing first selection signals identifying said predetermined ones of said functional signal groupings; and second selection means coupled to said first selection means and to a second group of predetermined ones of said stages for providing read-probe pulse selection signals in response to said function signal groupings.

Claim 13

An improved programmably alterable memory timing system as in claim 10 wherein said read-probe pulse generating means includes timing means coupled to said second selection means for providing programmably selected read-probe pulses for said gating of data signals at the programmably selected times in response to said read-probe pulse selection signals.

Claim 14

An improved programmably alterable memory timing system as in claim 9 wherein said times of occurrence of said read-probe pulses include at least normally-timed read-probe pulses, early-timed read-probe pulses and late-timed read-probe pulses separately selectable by associated ones of said predetermined ones of said function signal groupings, and said second selection means includes early read-probe pulses selection means for providing early read-probe pulse selection signals, normal read-probe pulse selection means for providing normal read-probe pulse selection signals, and late read-probe pulse selection means for providing late read-probe pulse selection signals.

Claim 15

An improved programmably alterable memory timing system as in claim 12 wherein said read-probe pulse generating means includes first timing means coupled to said early read-probe pulse selection means for generating read-probe pulses a predetermined time earlier than normally-timed read-probe pulses in response to said early read-probe pulse selection signals, second timing means for generating said normally-timed read-probe pulses in response to said normal read-probe pulse selection signals, and third timing means for generating read-probe pulses a predetermined time later than said normally-timed read-probe pulses in response to said late read-probe pulse selection signals.

Claim 16

An improved memory system including magnetic memory means having reading means for reading recorded signals and read-probe gating means coupled to said reading means for timing the reading of said recorded signals; and programmable control means coupled to said read-proBe gating means for programmably determining the time of occurrence of read-probe pulses for enabling said read-probe gating means.

Claim 17

An improved memory system including magnetic memory means having reading means for reading recorded signals and read-probe gating means coupled to said reading means for timing the reading of said recorded signals; and programmable control means coupled to said read-proBe gating means for programmably determining the time of occurrence of read-probe pulses for enabling said read-probe gating means.

Claim 18

An improved memory system as in claim 14 wherein said read-probe gating means includes a plurality of timing circuits, each of said timing circuits establishing a predetermined time of occurrence of said read-probe pulses.